Speech detector circuit with associated gain control for a tasi

Multiplex communications – Wide area network – Packet switching

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Details

179 1555T, 370 81, H04J 602

Patent

active

043529577

ABSTRACT:
Disclosed is a centralized circuit for determining whether input signals from a plurality of channels are speech which includes memory means in which digital amplitude samples from each of the input channels are stored in real time. A control means then periodically retrieves the samples from the memory in a time faster than real time and produces a series of time compressed input signals which are compared with a variable threshold derived from a stored level for each channel. Moreover, means are disclosed for setting a new threshold whenever the time compressed input signals differs from the old level for a predetermined time, the new level thereafter being stored in place of the previously stored old level.

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