Speculative load instruction rescheduler for a compiler which mo

Details Speculative load instruction rescheduler for a compiler which mo Speculative load instruction rescheduler for a compiler which mo

1994-12-27

1996-06-11

Lall, Parshotam S.

Boots, shoes, and leggings

395700, 364DIG1, G06F 945

Patent

active

055264999

ABSTRACT:
An instruction scheduler for a computer, capable of speculatively scheduling load instructions by moving certain categories of load instructions in an input instruction sequence from a source block of instructions to a target block of instructions to form an output instruction sequence, the instruction scheduler comprising: logic for selecting a data-independent load instruction as a candidate for rescheduling; logic for determining whether the base register that the load instruction makes use of and/or the contents thereof meets any one of a number of conditions; logic for moving the selected load instruction from the source block to the target block in response to determination that any one of the conditions is met.

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"The Metaflow Architecture", Popescu et al, IEEE 1991, pp. 10-73.
"Organization of the Motorola 88110 Superscalar RISC Microprocessor" Diefendorff et al, IEEE 1992, pp. 40-63.
"A VLIW Architecture for a Trace Scheduling Compiler", Colwell et al, IEEE, vol. 37, No. 8, Aug. 1988, pp. 967-979.

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