Speculative execution for data ciphering operations

Details Speculative execution for data ciphering operations Speculative execution for data ciphering operations

2007-08-21

2007-08-21

Moazzami, Nasser (Department: 2136)

Cryptography

Communication system using cryptography

Time segment interchange

C380S036000

Reexamination Certificate

active

10092328

ABSTRACT:
In one embodiment, a computer-implemented method comprises receiving a data cipher operation. The method also comprises processing the data cipher operation. The processing of the operation includes generating a number of portions of ciphertext from plaintext, wherein a load operation associated with the generating of at least one portion of the ciphertext executes prior to a store operation associated with the generating of a prior portion of the ciphertext.

REFERENCES:
patent: 4078152 (1978-03-01), Tuckerman, III
patent: 5016275 (1991-05-01), Smith
patent: 5301235 (1994-04-01), Shimada
patent: 5444781 (1995-08-01), Lynn et al.
patent: 5454117 (1995-09-01), Puziol et al.
patent: 5572707 (1996-11-01), Rozman et al.
patent: 5754812 (1998-05-01), Favor et al.
patent: 5794061 (1998-08-01), Hansen et al.
patent: 5799165 (1998-08-01), Favor et al.
patent: 5801975 (1998-09-01), Thayer et al.
patent: 5826073 (1998-10-01), Ben-Meir et al.
patent: 5835599 (1998-11-01), Buer
patent: 5884059 (1999-03-01), Favor et al.
patent: 5919256 (1999-07-01), Widigen et al.
patent: 5926642 (1999-07-01), Favor
patent: 6047372 (2000-04-01), Thayer et al.
patent: 6061521 (2000-05-01), Thayer et al.
patent: 6154831 (2000-11-01), Thayer et al.
patent: 6185304 (2001-02-01), Coppersmith et al.
patent: 6185679 (2001-02-01), Coppersmith et al.
patent: 6189095 (2001-02-01), Coppersmith et al.
patent: 6192129 (2001-02-01), Coppersmith et al.
patent: 6195744 (2001-02-01), Favor et al.
patent: 6202204 (2001-03-01), Wu et al.
patent: 6223276 (2001-04-01), Lee et al.
patent: 6226742 (2001-05-01), Jakubowski et al.
patent: 6243470 (2001-06-01), Coppersmith et al.
patent: 6249582 (2001-06-01), Gilley
patent: 6332214 (2001-12-01), Wu
patent: 6347143 (2002-02-01), Goff et al.
patent: 6356270 (2002-03-01), Pentkovski et al.
patent: 6369813 (2002-04-01), Pentkovski et al.
patent: 6421730 (2002-07-01), Narad et al.
patent: 6459792 (2002-10-01), Ohmori et al.
patent: 6463579 (2002-10-01), McKinsey
patent: 6539541 (2003-03-01), Geva
patent: 6549622 (2003-04-01), Matthews, Jr.
patent: 6598156 (2003-07-01), Arora
patent: 6643745 (2003-11-01), Palanca et al.
patent: 6658559 (2003-12-01), Arora et al.
patent: 6658578 (2003-12-01), Laurenti et al.
patent: 6681317 (2004-01-01), Mathews
patent: 6704871 (2004-03-01), Kaplan et al.
patent: 6728867 (2004-04-01), Kling
patent: 6873707 (2005-03-01), Batcher
patent: 2001/0025341 (2001-09-01), Marshall
patent: 2002/0004904 (2002-01-01), Blaker et al.
patent: 2002/0194483 (2002-12-01), Wenocur et al.
patent: 2002/0196935 (2002-12-01), Wenocur et al.
Bruce Schneier, Doug Whiting, Fast Software Encryption: Designing Encryption Algorithms for Optimal Software Speed on the Intel Pentium Processor, Lecture Notes in Computer Science, vol. 1267, Jan. 1997, p. 242.
Mosanya et al., CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor, 1999, Springer Verlag Berlin, pp. 246-256.
Wollinger et al., How Well Are High-End DSPs Suited for the AES Algorithms?, Apr. 2000, Texas Instrument.
Shehata et al., VLSI Implementation of a High Speed Block-Cipher Module, 2001, IEEE.
Chodowiec et al., Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining, Feb. 2001, ACM.
Hong et al., Hardware Design and Performance Extimation of the 128-bit Block Cipher CRYPTON, 1999, Springer-Verlag Berlin, pp. 49-60.
McLoone et al., Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm, 2001, Springer-Verlag Berlin, pp. 152-161.
Moldovyan et al., A Cipher Based on Data-Dependent Permutations, Aug. 2001, Journal of Cryptology, pp. 61-72.
Lin et al., A VLSI Implementation of the Blowfish Encryption/Decryption Algorithm, 2000, IEEE.
Childers et al., Architectural Considerations for Application-Specific Counterflow Pipelines, Mar. 1999, IEEE, Advanced Research in VLSI.
Sherigar et al., A pieplined parallel processor to implement MD4 message digest algorithm on Xilinx FPGA, Jan. 1998, IEEE, Eleventh International Conference on VLSI Design, pp. 394-399.
Craig Clapp, Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors, 1997, Proceedings of Fast Software Encryption Workshop.
Ye et al., CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit, 2000, IEEE, Proceedings of the 27th International Symposium on Computer Architecture, pp. 225-235.
Ian Goldberg and David Wagner. Architecture Considerations for Cryptanalytic Hardware. CS252 Report, May 1996. <http://citeseer.ist.psu.edu/goldberg96architectural.html>.
Fluhrer, S., et al., “Attack on RC4 and WEP,” Cryptobytes 2002, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, 9 pages.
Fluhrer, S., et al., “Statistical Analysis of the Alleged RC4 Keystream Generator,” FSE 2000, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, 12 pages.
Fluhrer, S., et al., “Weakness in the Key Scheduling Algorithm of RC4,” SAC 2001, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, 23 pages.
Golic, Jovan D., “Linear Statistical Weakness of Alleged RC4 Keystream Generator,” EUROCRYPT 1997, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, pp. 226-238.
Grosul, A. L., et al., “A Related-Key Cryptanalysis of RC4,” Jun. 6, 2002, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, pp. 1-13.
Knudsen, L.R., et al., “Analysis Methods for (Allegd) RC4,” ASIACRYPT 1998, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, 15 pages.
Mantin and Shamir, “A Practical Attack on Broadcast RC4,” FSE 2001, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, 13 pages.
Schneier, B., Applied Cryptography, Second Edition, published by John Wiley & Sons, Inc., 1996, ch. 17 “Other Stream Ciphers and Real Random-Sequence Generators,” pp. 397-398.
Stubblefield, A., et al., “Using the Fluhrer, Mantin, and Shamir Attack to Break WEP,” AT&T Labs Technical Report TD-4ZCPZZ, Aug. 6, 2001, http://www.wisdom.weizmann.ac.il/˜itsik/RC4/rc4.html, 9 pages.
RSA Laboratories, Cryptography FAQ, What is RC4? http://www.rsasecuirty.com/rsalabs/faq/3-6-3.html, Jan. 30, 2002, 1 page.

Affiliated with

Also associated with

Rating

Speculative execution for data ciphering operations does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Speculative execution for data ciphering operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Speculative execution for data ciphering operations will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3896153