Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Analysis of complex waves
Patent
1996-12-23
1998-12-08
Regan, Maura
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Analysis of complex waves
455 671, 324 7623, 702 66, G01R 2726
Patent
active
058475591
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a local oscillator to be used in a spectrum analyzer, and more particularly, to a local oscillator which reduces dynamic spurious caused by a digital step sweep of the local oscillator.
BACKGROUND ART
An example of conventional spectrum analyzer utilizes a local oscillator whose frequency is digitally controlled by a step sweep signal through a direct digital synthesizer (DDS) technology. This example is explained with reference to FIGS. 4, 5 and 6.
This analyzer is formed of, as shown in FIG. 4, a frequency converter 50, a detector 62, display arithmetic unit 64, and a display 68.
The frequency converter 50, as used as a frequency converter in an ordinary spectrum analyzer, receives a input signal 100 to be analyzed and converts the input signal to an intermediate frequency signal when a local oscillator sweeps its frequency for selected frequency ranges. The intermediate frequency signal is filtered by a BFP (band pass filter) to a predetermined band width and is then provided to the detector 62. The frequency converter 50 includes an ATT (attenuator) 51, mixers 52 and 53, a local oscillator 30, an oscillator 54 and a BFP 55.
The local oscillator 30 is an oscillator which can sweep a desired frequency range in a digital step manner with the use of DDS. As shown in FIG. 5, the local oscillator 30 includes a DDS time base 32, a DDS 40, a DA converter 34, LPF (low pass filter) 35, a phase comparator 36, a divider 37, an integrator 38, and a YTO (YIG-tuned oscillator) 39.
The DDS time base 32 receives a reference clock 31 and sweep conditions 33 which includes a span (sweep frequency range) and a sweep time T.sub.sweep and delivers a clock signal 32.sub.clk to the DDS 40. The clock signal 32.sub.clk has a unit time step T.sub.step which is produced by dividing the reference clock 32 by a division factor Div, i.e., T.sub.step =Div/(reference clock 31). Thus, one clock time period of the clock signal 32.sub.clk is the unit time step Tstep for the step sweep of the local oscillator 30.
The DDS 40 is a synthesizer which generates a data signal indicating a desired frequency of a digital sine wave in a digital form. As shown in FIG. 6, the DDS 40 is formed of a frequency register 42, an adder 44, and a ROM table memory 46.
The frequency register 42 stores advanced phase data 42.sub.dat and provides the phase data to one input of the adder 44. The advance phase data defines an advanced phase of a sine wave expressed by 32 bit data. By this data, as shown in a stepped ramp signal of FIG. 7(a), a unit step frequency 92 is accumulated at every unit step time T.sub.step, which results in one sweep time T.sub.sweep =M.times.T.sub.step. Here, M is a constant number of steps in a sweep, such as M=2,048.
The adder 44 is a 32 bit accumulator to advance the unit phase of the above noted unit frequency 92 of the sine wave. At every clock signal 32.sub.clk from the DDS time base 32, one input terminal of the adder 44 receives the advance phase data 42.sub.dat, while the other input terminal receives the data from a register 44.sub.r which holds the value in the previous accumulation cycle. The adder 44 accumulates the two input data and the result is latched in the register 44.sub.r.
The ROM table memory 46 converts the received data to the code of step like sine waveform data. The ROM table memory 46 uses upper 10 bit data out of 32 bit data from the adder 44 as address data to read out 10 bit sine wave code data 46.sub.dat from the table memory. The sine wave code data 46.sub.dat is supplied to the DA converter 34 shown in FIG. 5.
The DA converter 34 in FIG. 5 converts the 10 bit sine wave code data 46.sub.dat to a step like analog signal. The LPF 35 removes frequency components of the clock signal 32.sub.clk in the step like analog signal to make a sine wave analog signal and provides the sine wave analog signal to one input terminal of the phase comparator 36.
A PLL (phase lock loop) control loop is formed of the YTO 39, the divider 37, the phase comparator 36, and the integra
REFERENCES:
patent: 4581767 (1986-04-01), Monsen
patent: 4678345 (1987-07-01), Agosten
patent: 4795970 (1989-01-01), Owen
patent: 4799020 (1989-01-01), English
patent: 4998217 (1991-03-01), Holcomb
Fukui Takayoshi
Takaoku Hiroaki
Advantest Corp.
Regan Maura
LandOfFree
Spectrum Analyzer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Spectrum Analyzer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Spectrum Analyzer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-181598