Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2000-01-05
2002-03-19
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C257S758000, C257S759000
Reexamination Certificate
active
06358777
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit manufacture and, more particularly, to the formation of metal interconnect structures for integrated circuits. A major objective of the present invention is to improve trench-depth precision in a dual-damascene process often used for making copper interconnect structures.
Much of modem progress is associated with the increasing prevalence of computers, which has, in turn, been made possible by advances in integrated-circuit manufacturing technology. These advances have led to ever shrinking dimensions for circuit elements. This shrinking has made it possible to place more circuit elements on a single integrated circuit for greater functionality. In addition, the circuits are closer together so that communication among circuit elements can be faster.
A typical integrated circuit comprises a semiconductor substrate in which circuit elements are formed, a submetal structure that can include transistor gates and contacts, as well as local interconnects, a submetal dielectric, and a metal interconnect structure. The metal interconnect structure is typically formed by depositing metal (for conducting signals) and dielectric (for electrically separating conductors), and patterning the deposited materials photolithographically.
For many years, aluminum has been the metal of choice for interconnect structures since it is a good conductor, it is readily patterned, and it is process compatible with the other materials involved integrated-circuit manufacture. However, as features sizes fall to deep submicron levels, the resistance of aluminum becomes a salient factor in limiting device performance. (The resistance of a conductor is inversely proportional to its cross section, which drops with reductions in both width and thickness of a conductor. A high resistance causes high-frequency electrical energy associated with fast integrated circuits to be dissipated as heat.) To overcome this limitation, integrated circuits have turned to a lower-resistance metal—copper.
While it addresses the problem of resistance, the use of copper introduces additional problems. Copper is relatively hard to pattern; however, a damascene process has been developed to address this problem. Another problem is that copper ions have a deleterious affect if allowed to migrate into the semiconductor substrate. To address this problem, barrier metal, such as tantalum, is used to encapsulate copper conductors to prevent the migration.
The damascene process involves depositing a silicon dioxide layer, patterning that layer to form trenches, depositing a conforming layer of barrier metal, depositing copper to overfill the trenches, and polishing the copper until it is flush with the silicon dioxide. In accordance with a “dual-damascene” process, vias can be formed by masking the patterned silicon dioxide before the barrier metal is deposited and etching apertures through silicon dioxide below the trenches where the vias are to be formed. The barrier metal is then deposited so that it conforms to the via apertures as well as the trenches. The copper then fills the via apertures as well as the trenches so that a single deposition provides for both conductors and vias.
Trench depth is a critical parameter. Trench depth corresponds to the eventual conductor thickness. Excessive variation in metal thickness can cause unpredictable timing. In addition, if the trenches are too shallow via apertures from the trench down to the underlying metal can be too deep. In that case, the via apertures can have excessively high height-to-width aspect ratios; this can make it difficult for the barrier metal and copper depositions to conform properly to the underlying surfaces. As a result of poor conformity, electrical connections can be impaired. Finally, if the trenches are too deep, the underlying dielectric may be so thin that its integrity is compromised; the result can be a premature dielectric breakdown, adversely affecting device performance lifetime.
The formation of trenches in a damascene process is not the only case in which etch depth is critical. However, in many cases, the goal of an etch is to expose a material that is different from the material being etched. Where the etch is to expose a different material, there are several approaches available to control etch depth. One approach detects when the different material is exposed. Sometimes this can be done by optically monitoring the surface being etched. In the case of a plasma etch, the plasma composition changes as it begins to etch the underlying material. The etching can then be detected by monitoring the spectral characteristics of the plasma itself.
Another approach, which can be combined with detection, is to use a differential etchant technique. If the etching process etches the overlaying material much faster than the underlying material, then the etch depth is less time critical as long as the underlying material is exposed. The differential etchant approach is particular useful for chemical etching where there are a number of etchants available with very different interactions with different materials.
As feature sizes have decreased, the use of chemical etchants has been reduced in favor of plasma etches. If a plasma does not etch the underlying material much slower than the overlying material, depth control becomes problematic. One solution is to “coat” the underlying material with an etch-resistant material, which then serves as an “etch stop”. For example, silicon nitride can be used as an etch stop when etching silicon dioxide over polysilicon since silicon nitride has the slowest plasma etch rate of the three.
However, the use of a silicon-nitride etch stop in the context of a dual-damascene process is not favored since the silicon nitride has a substantial higher (7.0 versus 4.0) dielectric constant than silicon dioxide. The presence of silicon nitride would thus increase capacitance. The resulting performance impairment would offset much of the advantage achieved in lowering resistance by using copper instead of aluminum.
Accordingly, the prevailing method of controlling trench depth relies on timed etches based on estimated etch rates. While timed etches can be precise for shallow etches, the trenches involved in the dual-damascene process have depths that correspond to the desired conductor thicknesses. At such depths, the precision of the timed etches is not optimal. What is needed is a method that allows for more precise trench depths and, thus, more reliable copper-based integrated circuits.
SUMMARY OF THE INVENTION
The present invention involves the use of a marker layer with a dielectric constant lower than that of silicon dioxide to indicate when an etch is to be stopped. While overlaying silicon dioxide is being etched by a plasma, the optical spectrum of the plasma is monitored for the presence of an ionic form of a constituent of the marker layer that is not silicon or oxygen or any gas used to form the bulk of the plasma. The presence of the constituent in the plasma spectrum indicates that the marker layer is being etched. The etching can be terminated as a function of the detection of this constituent.
The method of the invention involves forming a lower silicon dioxide layer over a lower patterned metal, e.g., copper, layer. The low-k dielectric marker layer is deposited on the lower silicon-dioxide layer. An upper silicon dioxide layer is deposited over the low-k marker layer. The resulting structure is masked using an upper metal layer pattern, for example by using photoresist according to conventional photolithograpy. A plasma etch is performed through the trench-pattern mask.
During the plasma etch, the optical spectrum of the plasma is monitored in such a way that etching of the marker layer can be detected. For example, the marker layer can consist of fluorinated silicon oxide (SiOF). In this case, a spectral frequency associated with fluorine ions (and not with silicon or oxygen ions) can be monitored. When the etch reaches the marker layer, the spectr
Chaudhuri Olik
Ha Nathan W.
Philips Electronics No. America Corp.
Zawilski Peter
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