Special test modes for a page buffer shared resource in a memory

Details Special test modes for a page buffer shared resource in a memory Special test modes for a page buffer shared resource in a memory

1993-06-30

1997-04-22

Lane, Jack A.

395428, 395430, 395419, G06F 1202

Patent

active

056236204

ABSTRACT:
A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

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