Special accumulate instruction for multiple floating point arith

Details Special accumulate instruction for multiple floating point arith Special accumulate instruction for multiple floating point arith

1984-10-25

1987-07-28

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 738

Patent

active

046835474

ABSTRACT:
A data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions. These instructions are separated by add operations, including passing the results of each multiply/divide operation on a bypass bus to the input of an adder along with the inputs from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation. This allows two floating point results to be produced each cycle, one of which can be accumulated without any intervening control by the central decoder. The accumulation is performed under distributed control of the accumulator logic itself.

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