Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Parallel controlled paths
Reexamination Certificate
2001-11-28
2003-02-25
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Parallel controlled paths
C326S010000
Reexamination Certificate
active
06525590
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to electronic circuits, and is particularly directed to a spatial and complementary semiconductor device-containing, redundancy-based circuit architecture, that is configured to prevent one or more upset events, such as those produced by the incidence of cosmic rays and the like, present in airborne and spaceborne environments, from perturbing or modifying the intended value of an electrical parameter at an output port of the circuit. To provide resistance to such upset events, the present invention couples multiple copies of a complementary semiconductor device based circuit between input ports and the output port, such that the intended value of the electrical parameter will be sustained by one of the multiple copies of the multiple copies at which the upset event does not occur.
BACKGROUND OF THE INVENTION
Semiconductor circuits employed in environments prone to incidence of cosmic rays or high energy particles can be disturbed or interrupted by charge deposit anomalies associated with such incidence, resulting in what are commonly termed single event effects (SEEs), including single event upsets (SEUs) for digital circuits, and single event transients (SETS) for analog circuits. Typical, but non-limiting examples of applications that are subject to such events or upsets include spaceborne systems, as well as airborne and terrestrial systems that operate in the vicinity of the earth's magnetic poles. Moreover, as improvements in semiconductor manufacturing techniques continue to reduce feature size (and thus increase integration density), there is an escalating probability of single event effects in such systems.
Up to the present, the major industry focus has been upon the digital arena, particularly on digital signal processing applications, where a single bit error caused by an SEU may cause substantial corruption of the operation of an entire digital system. Efforts to combat the SEU problem in digital applications have included installation of redundant or parallel systems (including separately clocked or sampling schemes), coupled with majority voting techniques to ‘mask’ out effects of such event upsets.
In contrast, industry efforts to address the potential impact of SEEs on the operation of analog systems have not produced an effective and reliable working solution. However, as increasing numbers of electronic systems, such as high data rate communication systems, are implemented as an integration of high density analog and digital components in a common support and signal feed and distribution architecture, SEE anomalies in analog components may propagate and thereby corrupt downstream digital components, especially in spaceborne and airborne systems.
SUMMARY OF THE INVENTION
In accordance with the present invention, this SEE problem in analog circuits is effectively obviated by means of a new and improved spatial and complementary semiconductor device, redundancy-based analog circuit architecture, that is configured to prevent one or more single event effects (single event transients) from modifying the intended value of an electrical parameter at an output port of an analog circuit.
For this purpose, the invention couples at least one and preferably multiple redundant spatially separate copies of the analog circuit (such as a voltage reference or an operational amplifier) between input ports and the circuit's output port, via a complementary semiconductor device-encountering path. The architecture is configured such that the likelihood of a single particle passing through multiple circuits at the same time is rendered extremely remote, and such that the intended value of the electrical parameter will be sustained at the output port by either the given circuit itself or any of the redundant copies of the circuit at which the SEE does not occur.
A non-limiting example of such an analog circuit is a buffer (operational) amplifier configuration preferably configured as a triple amplifier scheme, having a pair of parallel-coupled complementary semiconductor circuits, and providing immunity against the unlikely occurrence of two simultaneous SEEs, without excessively increasing circuit occupancy of available chip real estate. A respective amplifier of a triple amplifier set has two inputs coupled to a different pair of three input lines, each of which is associated with a desired input, but may be perturbed by an SEE.
As will be described, the invention employs complementary semiconductor polarity input and output devices (e.g., NPN and PNP bipolar transistors) for each amplifier set, as well as complementary semiconductor device-based architectures of each pair of amplifier triplets. These circuits are connected in parallel to realize immunity against either a high-to-low or a low-to-high perturbation on any two of the three input lines. The architecture is such that one of a three amplifier set to which an unperturbed (e.g., by an SEE) voltage is applied will also effectively decouple the output node from an SEE-based perturbation (voltage spike) applied to that amplifier set, whereas the unperturbed voltage itself will be properly coupled to the output node, thereby ensuring SEE-immunity.
In a further embodiment of the invention, three input lines of the triple amplifier architecture are coupled to outputs of three respective differential amplifiers of a front end differential amplifier block. These front end differential amplifiers have their respective differential inputs coupled in parallel to differential polarity input nodes. The multiple redundancy provided by the front end differential amplifiers coupled with that of a cascaded triple amplifier scheme described above allows for the simultaneous occurrence of a single event transient (e.g. pulse/spike) of either polarity for any two of the front end differential amplifiers, without changing the intended state of the output node from that provided by the unperturbed amplifier within the cascaded triplet. This provides a very robust immunity to events that are capable of producing transients of either polarity.
REFERENCES:
patent: 3979720 (1976-09-01), Laas et al.
patent: 4839855 (1989-06-01), Van Driel
patent: 4920309 (1990-04-01), Szepesi
patent: 5903717 (1999-05-01), Wardrop
patent: 5923830 (1999-07-01), Fuchs et al.
patent: 6098929 (2000-08-01), Falbel
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6141770 (2000-10-01), Fuchs et al.
patent: RE37739 (2002-06-01), Sutardja et al.
Aviation Week & Space Technology/Jul. 30, 2001, Inside Avionics, Edited by Bruce D. Nordwall, p. 49.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Intersil America's Inc.
Nu Ton My-Trang
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