Spatially offset deep trenches for high density DRAMS

Details Spatially offset deep trenches for high density DRAMS Spatially offset deep trenches for high density DRAMS

1999-09-01

2001-04-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S386000

Reexamination Certificate

active

06214686

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and methods of manufacturing the same, and more particularly, to a method and device structure for forming storage nodes for a one transistor, one capacitor memory cell.
2. Description of the Related Art
As the capacity of semiconductor memory devices such as dynamic random access memories (DRAMs) is increased, various ways have been proposed to increase the integration density of memory cells. A one transistor, one capacitor cell structure is generally used for DRAMs. The one transistor, one capacitor cell is most suitable for high integration since the memory cell is formed by a small number of elements. Various types of capacitor structures for DRAMs are known, such as planar structures, stack structures and buried plate type trench capacitors. The desire is to obtain a large amount of memory capacitance using as small of a planar area on an integrated circuit substrate as possible.
A memory cell of a buried plate type DRAM is an example of an arrangement in which a storage capacitance is formed 3-dimensionally. In such a memory cell, a deep trench is formed in a silicon substrate in a direction perpendicular to the main semiconductor device thereof and the memory capacitor is formed on the sidewall of the trench. Therefore, the cell area can be smaller as compared to the planar capacitor type DRAM. Such deep trench based storage devices are typically etched up to 8 microns deep into the silicon. The process used for forming the deep trenches may differ between various memory sizes such as 4 megabits, 16 megabits, 256 megabits and 1 gigabit DRAM arrays. However, there are a given number of process steps that are common to each generation of DRAM cells. The commonly performed deep trench processing steps which constitute a large portion of the cost of making each of these trench-based cells are as follows: the etching of the deep trench, the formation of the initial node dielectric followed by low pressure chemical vapor deposition (LPCVD) of silicon nitride, the reoxidation of the node dielectric, the deposition of a first polysilicon fill using LPCVD, the chemical mechanical polish of the first polysilicon fill, the etching of a first recess in the first polysilicon fill using reactive ion etching (RIE), the deposition of a collar oxide, the etching of the collar oxide using RIE, the deposition of a second polysilicon fill using LPCVD, and a chemical mechanical polish of the second polysilicon fill. The method for forming a storage node for deep trench-based DRAM is disclosed in U.S. Pat. No. 5,656,535, issued Aug. 12, 1997 to Ho et al., the teachings of which are fully incorporated herein by reference.
Recent innovations in trench cell formation include the formation of a buried plate to reduce the voltage dropped across the node dielectric. This allows the use of a nitride-oxide (NO) dielectric node which are typically used for 256 Mb DRAMs.
Advanced 256 Mb and 1 Gbit trench cells also use a LOCOS collar (instead of the conventional collar process described above) which facilitates trench enhancement below the LOCOS collar and a self aligned buried plate. This technique is disclosed in the above referenced U.S. Pat. No. 5,656,535, the teachings of which are herein incorporated by reference.
In addition, even when using memory cell layouts that are designed to be below the conventional eight times the minimum full lithographic feature (8F
2
) in square area, it is necessary to maximize the storage node capacitance for each subsequent lithography generation. In order to facilitate this need for increased capacitance, the present invention teaches a method to form spatially offset deep trenches which are compatible with all previous techniques for trench capacitance enhancement.
SUMMARY OF THE INVENTION
The present invention is a method of fabricating a storage node for a deep trench DRAM on a semiconductor substrate. The method comprises etching a trench into a silicon substrate, then etching an adjacent trench into the substrate at a different depth and then forming bottle shaped enlargements within the trenches at vertically spaced offsets for adjacent trenches. A masking step is used to block initial trench etching for adjacent trenches to obtain different starting depth for formation of the bulbuous regions within the trenches. One or more bulbous enlargements may be formed within the vertical trench to obtain large capacitance nodes within a minimum memory cell area.


REFERENCES:
patent: 4502913 (1985-03-01), Lechaton et al.
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5629226 (1997-05-01), Ohtsuki
patent: 5656535 (1997-08-01), Ho et al.
patent: 5891807 (1999-04-01), Muller et al.
patent: 6071823 (2000-06-01), Hung et al.

Affiliated with

Also associated with

Rating

Spatially offset deep trenches for high density DRAMS does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Spatially offset deep trenches for high density DRAMS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Spatially offset deep trenches for high density DRAMS will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2532940