Image analysis – Histogram processing – For setting a threshold
Patent
1986-12-03
1988-05-24
Coles, Sr., Edward L.
Image analysis
Histogram processing
For setting a threshold
358 37, 358166, 358284, 382 54, 382 49, G06K 936
Patent
active
047471573
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a spatial product sum calculating unit, and more particularly to an arithmetic unit suitable for calculating the spatial product sum of each of a plurality of picture element data stored in a frame memory.
BACKGROUND ART
For the purpose of, for example, vividifying an image obtained by image sensing of an object with an imaging device, a spatial product sum calculation (a convolution) is performed for each picture element data of one frame which is a candidate for processing.
FIG. 7 is a diagram explanatory of a spatial product sum calculation with 3 rows and 3 columns. Where picture element data Fi,j and load coefficients Wi,j are arranged as shown, the result calculated of the spatial product sum, G2,2, for picture element data F2,2 is given by the following equation: ##EQU1## For convenience of description, calculations W1,1.times.F1,1+W2,1.times.F2,1+W3,1.times.F3,1, W1,2.times.F1,2+W2,2.times.F2,2+W3,2.times.F3,2, and W1,3.times.F1,3+W2,3.times.F2,3+W3,3.times.F3,3 in Eq. (1) will hereinafter be referred to as first, second and third calculations, respectively.
Conventionally, such a spatial product sum calculation as mentioned above is conducted through use of, for example, such devices as shown in FIGS. 8 and 9. The device depicted in FIG. 8 comprises one multiplier 1 and one integrator 2, in which the data Fi,j and the load coefficient Wi,j are sequentially entered into the one and the other input of the multiplier 1 to obtain Fi,j.times.Wi,j and the results of a total of nine calculations are integrated by the integrator 2.
The device shown in FIG. 9 comprises a total of nine multipliers 3.sub.1 to 3.sub.g and one adder 4, in which the multipliers receive the data Fi,j at one input and the different load coefficients Wi,j at the other input and perform parallel processing, the results of which are added together by the adder 4.
The device shown in FIG. 8 is small in the number of parts used, but requires much time for the spatial product sum calculation for each picture element data, and hence it is not suited for the calculation of the spatial product sums of, for example, 256.times.256 picture elements.
The unit depicted in FIG. 9 is capable of calculating the spatial product sum of each picture element data at a speed around nine times higher than the above device, but employs as many as nine bulky and expensive multipliers, and hence it is inevitably costly and large-sized, in general.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an arithmetic unit which permits a relatively high-speed calculation of the spatial produce sum for each of a plurality of picture element data stored in a frame memory, through use of a reduced number of multipliers.
According to the present invention, the above object is achieved by providing an arithmetic unit such, for example, as shown in FIG. 1, which calculates the spatial product sum for each of a plurality of picture element data stored in a frame memory 10, through utilization of load coefficients with N rows and N columsn prestored in a coefficient memory 12, and which comprises:
a first shift register having N stages;
N registers 13.sub.1 to 13.sub.n for setting therein N load coefficients;
N multipliers 14.sub.1 to 14.sub.n for multiplying the outputs of the registers 13.sub.1 to 13.sub.n and the corresponding stages 11.sub.1 to 11.sub.n of the first shift register 11;
a first adder for adding together the outputs of the N multipliers 14.sub.1 to 14.sub.n ;
a second shift register 17 having stages of the same number as the pieces of picture element data stored in the frame memory 10 in the row direction;
a second adder 16 for adding together the outputs of the first adder 15 and the second shift register 17, the added output being applied to the second shift register 17; and
a control circuit 18 which sets the load coefficients of one row of the coefficient memory 12 in the N register 13.sub.1 to 13.sub.n and effects control for all the rows of the coefficient memory 12 s
REFERENCES:
patent: 3905045 (1975-09-01), Nickel
patent: 4550437 (1985-10-01), Kobayashi et al.
Kurakake Mitsuo
Otsuka Shoichi
Coles Sr. Edward L.
Fanuc Ltd.
Parker Michael D.
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