Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
1998-06-12
2001-04-03
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S020000, C257S024000
Reexamination Certificate
active
06211530
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to devices that operate through the conduction of a very small number of electrical carriers and to methods of fabricating the devices.
BACKGROUND OF THE INVENTION
A relatively recent development in material science has been the ability to fabricate structures that are small on a quantum scale. On this small scale, 200 Å or less, the applicable physics is no longer that of the solid state bulk nor that of the gaseous free atom, but rather that of a quantum confined intermediate. Early in the development these small scale structures were formed in layers with confinement in one dimension only. The confined structures are typically composed of thin layers produced by MBE equipment on GaAs or other active substrates.
As an example of a use of these thin layers, lasers have been made that utilize the quantum confinement layers for carrier confinement or refractive optical confinement. In quantum-mechanically confined nanostructures, the degree of freedom in the free-electron motion decreases as N, the number of confined dimensions, goes up. This change in the electronic density of states has long been predicted to increase efficiency and reduce temperature sensitivity in lasers, and has been demonstrated for N=1 and 2. The techniques for the production of very thin layers of material with reasonable electronic mobilities require very meticulous crystal growth and exceedingly high purity.
For the ultimate case of N=3, there is also the occurrence of Coulomb blockade, a phenomenon that provides the basis for the operation of single-electron devices. Generally, a 3-D confined nanostructure is a small particle of material, e.g., semiconductor material, that is small enough to be quantum confined in three dimensions. That is, the quantum contained particle has a diameter that is only about 200 Å or less. This creates a three dimensional well with quantum confinement in all directions.
Traditionally, attempts to fabricate 3-D confined nanostructures relied on e-beam lithography. More recently, STM/AFM and self-assembled quantum dots (3-D confined nanostructures) have been fabricated. However, incorporating the 3-D confined nanostructures into a useful device is very difficult and has not been accomplished in a manufacturable process.
Accordingly, it would be very beneficial to be able to efficiently manufacture 3-D confined nanostructures in a useful device.
It is a purpose of the present invention to provide 3-D confined nanostructures in a useful device.
It is another purpose of the present invention to provide 3-D confined nanostructures in an inverter.
It is a further purpose of the present invention to provide a new and efficient method of manufacturing 3-D confined nanostructures.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in a sparse-carrier device including a crystal structure formed of a first material and having a crystallographic facet with contact structures at opposite ends of the length. Quantum dots are formed of a second material, using self-aligned techniques, and positioned in a plurality of rows on the crystallographic facet with each row extending along the length of the crystallographic facet and being approximately one quantum dot wide and a plurality of quantum dots long. The crystallographic facet is defined with a width to restrict formation of the second material thereon to the plurality of quantum dot wide rows of quantum dots. The quantum dots in a first row of the plurality of rows are separated from adjacent quantum dots in the first row by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in an adjacent row, and the quantum dots in the second row are separated from adjacent quantum dots in the second row by the first distance smaller than the second distance between the quantum dots in the second row and adjacent quantum dots in the first row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots along a row and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots between rows while being small enough to allow Coulombic interaction between adjacent quantum dots between rows. Electrical contacts are positioned on the contact structures at opposite ends of the rows with the electrical contacts being spaced from the quantum dots in the plurality of rows a distance to allow tunneling of carriers into and out of quantum dots in the plurality of rows.
In a specific application, a first row of the plurality of rows of quantum dots is connected to receive input signals and a second parallel spaced apart row of the plurality of rows of quantum dots is connected to provide an output signal. The quantum dots in the second row are charged oppositely to quantum dots in the first row by Coulombic interaction between adjacent quantum dots so that output signals from the second row are inverted from input signals supplied to the first row.
A method is disclosed of fabricating a sparse-carrier device including the steps of providing a crystal substrate of a first material and forming a crystal structure on the crystal substrate, the crystal structure being formed by growing a crystallographic facet of the first material with a predetermined width and length. Quantum dots of a second material are then selectively grown, using self-aligned techniques, in a plurality of rows on the crystallographic facet with each of the rows extending in parallel spaced apart relationship along the length of the crystallographic facet and being approximately one quantum dot wide and a plurality of quantum dots long. The plurality of rows of quantum dots are further selectively grown so that the quantum dots in a first row of the plurality of rows are separated from adjacent quantum dots in the first row by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in an adjacent second row, and the quantum dots in the second row are separated from adjacent quantum dots in the second row by the first distance smaller than the second distance between the quantum dots in the second row and adjacent quantum dots in the first row. Further, the first distance is small enough to allow carrier tunneling between adjacent quantum dots within each of the rows and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots between rows and small enough to allow Coulombic interaction between adjacent quantum dots between rows.
REFERENCES:
patent: 5614435 (1997-03-01), Petroff et al.
patent: 5783840 (1998-07-01), Randall
patent: 5888885 (1999-03-01), Xie
patent: 5905273 (1999-05-01), Hase
Goronkin Herbert
Shiralagi Kumar
Tsui Raymond K.
Zhang Ruth Y.
Jackson, Jr. Jerome
Koch William E.
Motorola Inc.
Parsons Eugene A.
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