Spare channel monitor circuit

Details Spare channel monitor circuit Spare channel monitor circuit

1988-12-19

1990-08-07

Fleming, Michael R.

Excavating

371 82, 371 51, G06F 1130

Patent

active

049473948

ABSTRACT:
In a monitor circuit, bipolar-to-unipolar (B/U) converters are respectively connected to spare channels to convert bipolar test signals of pseudo-random sequence received therethrough to RZ (return-to-zero) signals and thereafter to NRZ signals. Each B/U converter includes a clock recovery circuit recover clock pulses from the RZ signal. The original pseudo-random sequence is recovered from successive instants of the NRZ signal of each B/U converter in response to successive clock pulses. Divide-by-M counters are respectively connected to the clock recovery circuits to generate low frequency clock pulses, which drive D flip-flops to convert the bit pattern of each pseudo-random sequence so that the edges of the binary digits in the converted sequence has a sufficient timing margin with respect to a sampling point at which mismatch is detected between the sequences derived from the space channels. Detected mismatches are counted to indicate the signal quality and usage of the spare channels when the count exceeds a predetermined level during a specified time interval.

REFERENCES:
patent: 4658399 (1987-04-01), D'Angio
patent: 4760514 (1988-07-01), Hasegawa
patent: 4807226 (1989-02-01), Naka
patent: 4821267 (1987-04-01), Draegh

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