Sparce-redundant fixed point arithmetic modules

Details Sparce-redundant fixed point arithmetic modules Sparce-redundant fixed point arithmetic modules

2007-05-01

2007-05-01

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S493000, C708S620000

Reexamination Certificate

active

10348538

ABSTRACT:
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.

REFERENCES:
patent: 3535502 (1970-10-01), Clapper
patent: 4138731 (1979-02-01), Kamimoto et al.
patent: 5181186 (1993-01-01), Al-Ofi

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