Space-efficient semiconductor memory having hierarchical column

Details Space-efficient semiconductor memory having hierarchical column Space-efficient semiconductor memory having hierarchical column

1997-09-29

1999-07-13

Hoang, Huan

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365 63, 365 51, G11C 800

Patent

active

059236051

ABSTRACT:
Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL.sub.1 -GCSL.sub.(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.

REFERENCES:
patent: 5499215 (1996-03-01), Hatta
patent: 5715209 (1998-02-01), Yoo
patent: 5822268 (1998-10-01), Kirihata

Affiliated with

Also associated with

Rating

Space-efficient semiconductor memory having hierarchical column does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Space-efficient semiconductor memory having hierarchical column , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Space-efficient semiconductor memory having hierarchical column will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2283040