Space-efficient package for laterally conducting device

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame

Reexamination Certificate

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C257S666000, C257S784000, C257SE23037

Reexamination Certificate

active

07667309

ABSTRACT:
Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

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patent: 2002/0144396 (2002-10-01), Glenn
patent: 2004/0061205 (2004-04-01), Han et al.
International Search Report of PCT Application No. PCT/US03/40543, dated May 31, 2005, 4 pages total.

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