Space-efficient package for laterally conducting device

Details Space-efficient package for laterally conducting device Space-efficient package for laterally conducting device

2007-05-08

2007-05-08

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S784000, C257S786000, C257SE23037

Reexamination Certificate

active

10735585

ABSTRACT:
Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

REFERENCES:
patent: 5057805 (1991-10-01), Kadowaki
patent: 5289344 (1994-02-01), Gagnon et al.
patent: 5479050 (1995-12-01), Pritchard et al.
patent: 5631809 (1997-05-01), Takagi et al.
patent: 6831352 (2004-12-01), Tsai
patent: 2004/0061205 (2004-04-01), Han et al.

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