Space-efficient multi-cycle barrel shifter circuit

Details Space-efficient multi-cycle barrel shifter circuit Space-efficient multi-cycle barrel shifter circuit

2000-03-02

2001-11-06

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

C377S069000, C377S077000

Reexamination Certificate

active

06314156

ABSTRACT:

TECHNICAL FIELD
This invention pertains to the field of shifting digital data using combinatorial logic called “barrel shifters.”
BACKGROUND ART
A barrel shifter takes a data and a shift value as input and outputs the data shifted by the shift value. Conventional barrel shifters exist; however, conventional barrel shifters are typically implemented using fully combinatorial logic and perform the shift in a single cycle. Such conventional barrel shifters have several disadvantages.
First, the conventional, single cycle, fully combinatorial barrel shifters use more gates and take up more space on silicon than a smaller barrel shifter that uses less combinatorial logic.
Second, if the digital system in which the barrel shifter resides has multiple clock cycles to perform the shift operation, then the conventional barrel shifter is only being used at a fraction of its capacity if such conventional barrel shifter completes the task of shifting within a single clock cycle.
Given the foregoing, there is a need for a barrel shifter circuit that is space-efficient and that takes advantage of multiple clock cycles in order to perform the required shift operation.
SUMMARY OF THE INVENTION
The present invention includes a space-efficient multi-cycle barrel shifter circuit for shifting data by the inputted shift value. The present invention takes advantage of multiple clock cycles in order to perform the required shift. Rather than using a fully combinatorial, single cycle implementation of a barrel shifter, the present invention uses a barrel shifter circuit that is reduced in size and combinatorial logic, but that passes the data to be shifted through such barrel shifter circuit multiple times (once per clock cycle) with different, or in some cases the same, shift values. The sum of the shift value for each clock cycle will be the global shift applied to the data at a conclusion of a multi-cycle sequence. As the data is passed multiple times through the shifter circuit, the amount of shift after multiple passes (i.e., multiple clock cycles) will be greater than the amount of shift permissible from a single pass. Thus, the result is a space-efficient multi-cycle barrel shifter circuit.
A space-efficient multi-cycle barrel shifter circuit in accordance with the present invention may include a shift module, a load module, a register module and a control module, where the control module is coupled to the load module and the shift module, where the shift module is coupled to the register module and the load module, and where the register module is coupled to the load module. The shift module includes a shifter circuit that is smaller and uses less combinatorial logic than the conventional, fully combinatorial, single cycle implementation of a barrel shifter. The load module loads the data to be shifted into the barrel shifter circuit. The register module assists with passing the data to be shifted through the shift module once for each clock cycle. The control module computes the amount of shift imparted to the data through each cycle of the clock.


REFERENCES:
patent: 4962500 (1990-10-01), Nakagawa
patent: 5465223 (1995-11-01), Nishimura
patent: 5532949 (1996-07-01), Fujihara
patent: 5555202 (1996-09-01), Chu
patent: 5761266 (1998-06-01), Watts, Jr.
patent: 6078937 (2000-06-01), Vatinel

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