Space efficient low power cyclic A/D converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S155000

Reexamination Certificate

active

06909393

ABSTRACT:
Methods and apparatus are provided for an analog converter. The apparatus comprises a first redundant signed digit (RSD) stage and a configurable block. The configurable block converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage calculates a residue that is provided to the configurable block. The configurable block is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block is then converted back to a sample/hold circuit to start another conversion process.

REFERENCES:
patent: 5608402 (1997-03-01), Distinti
patent: 5644313 (1997-07-01), Rakers et al.
patent: 5995035 (1999-11-01), Signell et al.
patent: 6127958 (2000-10-01), Chang et al.
patent: 6380806 (2002-04-01), Ang
patent: 6535157 (2003-03-01), Garrity et al.
patent: 6778013 (2004-08-01), Ali

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