Space efficient column decoder for flash memory redundant column

Details Space efficient column decoder for flash memory redundant column Space efficient column decoder for flash memory redundant column

1996-12-17

1998-03-17

Nguyen, Hoa T.

Excavating

365200, 365201, G11C 2900

Patent

active

057295514

ABSTRACT:
The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The redundant column decoder has a pull-up path and a parallel combination of n pairs of complementary pull-down paths. The pull-up path is connected to the pull-down paths at an output node, and the output signal is taken at this output node. Each pair of complementary pull-down paths has a first pull-down path and a second pull-down path. The first pull down path has a first non-volatile memory cell in series with and connected to a first address transistor. The first address transistor is also connected to the output node. The second pull-down path has a second non-volatile memory cell in series with and connected to a second address transistor. The second address transistor is also connected to the output node. At least one of the pull-down paths is conductive when the stored defective address does not match the presented address. Conversely, all of the pull-down paths are non-conductive when the stored defective address matches the presented address.

REFERENCES:
patent: 4250570 (1981-02-01), Tsang et al.
patent: 5297085 (1994-03-01), Choi et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5471426 (1995-11-01), McClure

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