Space and process efficient MRAM

Details Space and process efficient MRAM Space and process efficient MRAM

2011-03-22

2011-03-22

Garber, Charles D (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C257S295000, C257SE21665, C257SE29323, C365S158000, C365S171000

Reexamination Certificate

active

07911013

ABSTRACT:
Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly on at least some of the source or drain regions without an intervening via. Embodiments of an MRAM array also include a first conductive interconnect layer above and in electrical contact with the upper electrodes of at least some of the MRAM bits, with no metal layers intervening between the upper electrodes and the first conductive interconnect layer.

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