Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-05-31
2011-05-31
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185230, C365S185250, C365S185330
Reexamination Certificate
active
07952929
ABSTRACT:
A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.
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Kim Jin-Ki
Pyeon Hong Beom
Borden Ladner Gervais LLP
Hung Shin
Mosaid Technologies Incorporated
Phan Trong
LandOfFree
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