Source regulation circuit for an erase operation of flash memory

Details Source regulation circuit for an erase operation of flash memory Source regulation circuit for an erase operation of flash memory

1997-04-18

2000-08-01

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518509, 36518529, 3651852, 36518533, G11C 1606

Patent

active

060976322

ABSTRACT:
A flash memory is described which uses floating gate transistors as memory cells. A source regulation circuit within the memory is described which generates a ramped reference voltage signal. The ramped reference voltage signal is applied to a differential amplifier connected to a reference circuit to produce a ramped erase voltage signal. The ramped erase voltage signal is then applied to sources of the memory cells during an erase operation. Both analog and digital circuits are described for generating the ramped reference voltage signal.

REFERENCES:
patent: 5315547 (1994-05-01), Shoji et al.
patent: 5568426 (1996-10-01), Roohparvar et al.
patent: 5619453 (1997-04-01), Roohparvar et al.
patent: 5627784 (1997-05-01), Roohparvar et al.
patent: 5636166 (1997-06-01), Roohparvar
patent: 5805502 (1998-09-01), Tang et al.

Affiliated with

Also associated with

Rating

Source regulation circuit for an erase operation of flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Source regulation circuit for an erase operation of flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Source regulation circuit for an erase operation of flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-670198