Source pre-charge system in a memory array

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36518911, 365203, 365204, G11C 700

Patent

active

055110320

ABSTRACT:
There is provided a memory array including columns of memory cells, source lines and bit lines. The memory array includes precharging apparatus which discharge selected source lines while pre-charging the array. Two embodiments of the pre-charging apparatus are provided. In both, the source lines are connected to a common bit line (CNBL) via groups of source pull-up transistors. The source lines are also connected to a source decoder. In one embodiment, the source decoder discharges selected ones of the disconnected source lines. In another embodiment, the source decoder both discharges selected ones of the disconnected source lines and connects the remaining disconnected source lines to the CNBL line.

REFERENCES:
patent: 4387447 (1983-06-01), Klaas et al.
patent: 4856106 (1989-08-01), Teraoka
patent: 4920516 (1990-04-01), Tsuchimoto
patent: 5182725 (1993-01-01), Andoh et al.

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