Source follower current mode logic cells

Details Source follower current mode logic cells Source follower current mode logic cells

1985-04-19

1988-03-01

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307471, 307497, 307559, H03K 19017, H03K 19086, G06F 750, G06G 712

Patent

active

047288213

ABSTRACT:
A source follower current steering logic circuit useful in, for example, fabricating digital integrated logic circuits using gallium arsenide and current mode logic switches. The circuit includes an input logic network which includes level shifting networks to generate output signals having assertion levels of different voltage levels and a reference voltage logic network having a similar level shifting network for generating reference voltages relative to the voltage levels of the assertion levels of the output signals from the input logic network. A logic tree includes current mode logic switches for receiving the output signals from the input logic network and the reference voltage generating network to perform selected logic operations the output signals. The output signals are taken from the logic tree. A top load clamps the output signals to selected voltage levels.

REFERENCES:
patent: 4393315 (1983-07-01), Stickel et al.
patent: 4412336 (1983-10-01), Peltier et al.
Electronics International, vol. 56, No. 17, Aug. 1983, pp. 71-72, New York, U.S.; J. Gosch "Cell Array Sports 230-ps Gate de Lay and 2,600 Functions".
Review of the Electrical Communication Laboratories, vol. 26, No. 9-10, Sep.-Oct. 1978, pp. 1339-1354; Y. Itou et al.: "ECL LSI Circuit Design".
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 3, Jun. 1984, pp. 299-305, New York, U.S.; E. Gouauser et al.: "A Bipolar 230 ps Master-Slice Cell Array with 2600 Gates".
IEEE Transactions on Microwave Theory and Techniques, vol. MTT-32, No. 1, Jan. 1984, pp. 5-10, New York, U.S.; Midda et al., "Analysis of High-Speed GaAs Source-Coupled FET Logic Circuits".
IEEE Electron Device Letters, vol. EDL-3, No. 8, Aug. 1982, pp. 197-199, New York, U.S.; S. Katsu et al.: "A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic".

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