Source electrode-connected type buffer circuit having LDD struct

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307450, H03K 19017, H03K 19094

Patent

active

053048709

ABSTRACT:
A buffer logic circuit having a lightly doped drain structure, comprising a power source potential, a ground potential, first and second Field Effect Transistors having drain electrodes, gate electrodes supplied with first input signal and a second input signal, respectively, source electrodes being connected to each other, and the drain electrodes for generating output signals corresponding to the input signals, respectively, device, having an end connected to the source electrodes of the first and second FETs, for reducing the potential of the drain electrodes, and device, connected between the other end of the drain electrode potential reducing device and the ground potential, for supplying a constant-current regulated power.

REFERENCES:
patent: 4044373 (1977-08-01), Nomiya et al.
patent: 4736117 (1988-04-01), Wieser
patent: 4968904 (1990-11-01), Yamashita et al.
patent: 5083046 (1992-01-01), Nagasawa
patent: 5128556 (1992-07-01), Hirakata
Chen, John Y.; "CMOS Devices and Technology For VLSI", .COPYRGT.1990 by Prentice-Hall, Inc.; pp. 199-210.

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