Source-coupled logic with reference controlled inputs

Details Source-coupled logic with reference controlled inputs Source-coupled logic with reference controlled inputs

1998-08-07

2001-05-08

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S078000

Reexamination Certificate

active

06229353

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital logic circuits and more particularly relates to a MOSFET source-coupled logic circuit which is faster, can be implemented with fewer transistors and avoids double-ended or complementary differential logic.
2. Description of the Related Art
This invention relates to source-coupled logic (SCL) which is a functional derivative of emitter-coupled logic (ECL). ECL is widely recognized as having the characteristics of high speed (low propagation delay) and low power supply noise generation. The SCL of the prior art succeeds at maintaining and improving the low noise characteristics of this architecture but does not fulfill the promise of high speed that one would expect from a current-mode logic. In addition, it uses a differential form of logic that is not as flexible and easy-to-use as a reference controlled or “single-ended” logic. The SCL disclosed here has the desired high speed properties and maintains the ease of use that is a property of reference controlled ECL. In addition, the reference controlled SCL of this invention provides new capabilities that make it even more flexible than ECL in generating logical switching functions.
A schematic diagram of a generic ECL inverter/buffer circuit is shown in FIG.
1
. For clarity, the pull-down resistors that are required at the outputs have been omitted. Descriptions of the operation of this circuit have been widely disseminated (including U.S. Pat. No. 3,259,761 and [1]). In essence, the input signal, V
IN
, is compared with a reference voltage, V
BB
, by a differential pair of matched bipolar junction transistors (BJTs), Q
1
and Q
2
. The relative values of V
IN
and V
BB
determine whether a bias current common to the emitters of Q
1
and Q
2
, I
EE
, is directed to one of two resistors, R
1
or R
2
. When V
IN
<V
BB
, this bias current flows through transistor Q
2
resulting in a voltage drop across resistor R
2
. This voltage is both buffered and level-shifted by an output emitter-follower transistor, Q
4
, resulting in a logic low voltage at the V
O
output. Simultaneously, the absence of any current flowing through R
1
results in a logic high voltage at the inverting output, V
O
—
N
. When V
IN
>V
BB
, the I
EE
bias current flows through transistor Q
1
causing a voltage drop across resistor R
1
rather than resistor R
2
. In this case, a low voltage, or logic 0, is developed at the inverting output, V
O
—
N
, while a high voltage, or logic 1, is developed at the non-inverting output, V
O
. A reference voltage, V
BB
, that is midway between the logic high and low voltages is supplied by an external bias circuit. A single bias circuit is usually shared by many ECL gate circuits. This bias circuit also regulates the value of I
EE
; typically by employing another BJT.
The essential aspects of a differential SCL gate are shown in FIG.
2
. (See U.S. Pat. No. 5,149,992 and [2-3].) The inverter/buffer shown here uses metal-oxide-semiconductor (MOS) field effect transistors (FETs) rather than BJTs but operation is similar. When V
IN
<V
IN
—
N
, the common source bias current, I
SS
, flows through transistor M
2
but not transistor M
1
developing a low voltage at the non-inverting output, V
O
, and a high voltage at the inverting output, V
O
—
N
. When V
IN
>V
IN
—
N
the opposite occurs: V
O
assumes a high, logic 1, voltage and V
O
—
N
assumes a low, logic 0, voltage. The logic input to this inverter/buffer gate consists of a pair differential of voltages, V
IN
and V
IN
—
N
, that each assume opposite states. While the use of two voltages to convey one signal can present several problems, it greatly simplifies the bias circuit. In fact, the bias circuit may be eliminated altogether if it is not necessary to closely regulate the value of I
SS
for optimum performance.
The circuit of
FIG. 2
assumes the use of enhancement mode N-type MOSFETs which typically have a positive threshold voltage that is of the same magnitude as the forward voltage of the NPN BJTs used in ECL circuits. It is also possible to perform logical switching functions by substituting FETs which have a lower threshold voltage, or even a negative threshold voltage (i.e., depletion mode FETS). Such source-coupled FET logic (SCFL) gates (see U.S. Pat. No. 3,783,400 and [4-5]) typically employ one or more forward biased diodes between the output source-follower transistors and their respective gate output terminals to increase the amount of voltage level-shifting provided. Otherwise, the operation of a SCFL gate is the same as that of a SCL gate.
Applicant cites the following art:
U.S. Patent Documents
3,259,761 7/1966 Narud et al. 307/88.5
5,149,992 9/1992 Allstot et al. 307/448
4,661,725 4/1987 Chantepie 307/450
Other Referrences
[1] Charles S. Meyer, David K. Lynn, and Douglas J. Hamilton,
Analysis and Design of Integrated Circuits,
McGraw-Hill Publishing Co., New York, 1968.
[2] Sayfe Kiaei, San-Hwa Chee and Dave Allstot, “CMOS Source-Coupled Logic for Mixed-Mode VLSI,” 1990 IEEE International Symposium on Circuits and Systems, vol. 2, pg. 1608-1611, IEEE, 1990.
[3] Dave J. Allstot, San-Hwa Chee, Sayfe Kiaei, and Manu Shrivastawa, “Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs,” IEEE Transactions on Circuits and Systems-I, vol. 40, no. 9, pg. 553-563, IEEE, September 1993.
[4] Stephen I. Long and Steven E. Butner,
Gallium Arsenide Digital Integrated Circuit Design,
McGraw-Hill Publishing Co., New York, 1990.
[5] S. Katsu, S. Nambu, A. Shimanoa and G. Kano, “A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic,” IEEE Electron Device Letters, vol. EDL-3, no. 8, pp. 197-199, August 1982.
[6]
An ECL and TTL Compatible Source
-
Coupled Logic Using Reference Controlled Inputs,
Paul M. Werking, thesis submitted for Master's Degree at The Ohio State University, June 1994.
SUMMARY OF THE INVENTION
The invention is a MOSFET logic circuit for connection between a pair of power buses for supplying power. It has a pair of source coupled input transistors, the gate of one forming the logic circuit input and the gate of the other connected to a bias circuit shared with other logic circuits and providing a reference voltage. First and second pull-up resistive circuits elements are connected between the respective different outputs of the input transistors and one bus. The different respective inputs of a pair of output transistors connected in a source-follower configuration are connected to the different respective outputs of the input transistors. A transistor, for conveying a constant current, is connected between the coupled input transistor sources and the other power bus and has its gate input connected to an external bias circuit shared by other such logic circuits for control of the constant current by the bias voltage applied to its gate.
The circuit may be enhanced by utilizing a MOSFET transistor as the resistive circuit elements with their gates connected to an external bias circuit shared by other such logic circuits for supplying a conductance controlling voltage. The circuit may also be enhanced by providing pull-down transistors each connected to the output of a respective different output transistor and controlled by a voltage supplied by an external bias connected to the input of each pull-down transistor.


REFERENCES:
patent: 3259761 (1966-07-01), Narud et al.
patent: 4661725 (1987-04-01), Chantepie
patent: 5149992 (1992-09-01), Allstot et al.
Meyer et al., Analysis and Design of Integrated Circuits, McGraw-Hill Publishing Co., NY, 1968.*
Kiaei et al., CMOS Source-Coupled Logic for Mixed-Mode VLSI, 1990 IEEE International Symposium on Circuits and Systems, vol. 2, p. 1608-1611, IEEE, 1990.*
Allstot et al., Folded Source-Coupled Logiv vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs, IEEE Transactions on Circuits and Systems-I, vol. 40, No. 9, pp. 553-563, Sep. 1993.*
Long et al., Gallium Arse

Affiliated with

Also associated with

Rating

Source-coupled logic with reference controlled inputs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Source-coupled logic with reference controlled inputs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Source-coupled logic with reference controlled inputs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2492382