Source centered clock supporting quad 10 GBPS serial interface

Details Source centered clock supporting quad 10 GBPS serial interface Source centered clock supporting quad 10 GBPS serial interface

2003-02-10

2009-08-18

Patel, Jayanti K (Department: 2419)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S463000, C370S537000

Reexamination Certificate

active

07577171

ABSTRACT:
A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

REFERENCES:
patent: 5490282 (1996-02-01), Dreps et al.
patent: 6667519 (2003-12-01), Farwell et al.
patent: 6674772 (2004-01-01), Dally et al.
patent: 7039067 (2006-05-01), Feinberg et al.
patent: 7106761 (2006-09-01), Shiota et al.
patent: 2002/0051468 (2002-05-01), Ofek et al.
patent: 2003/0043434 (2003-03-01), Brachmann et al.
patent: 2005/0229049 (2005-10-01), Collins

Affiliated with

Also associated with

Rating

Source centered clock supporting quad 10 GBPS serial interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Source centered clock supporting quad 10 GBPS serial interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Source centered clock supporting quad 10 GBPS serial interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4108836