Source biasing in non-volatile memory having row-based sectors

Details Source biasing in non-volatile memory having row-based sectors Source biasing in non-volatile memory having row-based sectors

1997-01-10

1999-07-13

Zarabian, A.

Static information storage and retrieval

Floating gate

Multiple values

36518518, G11C 1134

Patent

active

059235853

ABSTRACT:
A non-volatile memory includes an array of memory cells that is partitioned into sectors with sources of memory cells in each sector coupled together but electrically isolated from sources of memory cells in other sectors. Each sector includes one or more rows of memory cells, and sources of memory cells in each row are coupled together by a source-line. During programming of a selected memory cell, a bias circuit grounds a source-line in the sector containing the selected memory cell and applies a bias voltage to the source-lines in the other sectors. The bias voltage reduces program disturb of memory cells that are connected to the same bit-line as the selected memory cell. The bias circuit is coupled to address decode circuitry that indicates which source-line should be grounded.

REFERENCES:
patent: 5428568 (1995-06-01), Kobayashi
patent: 5521864 (1996-05-01), Kobayashi et al.
patent: 5612913 (1997-03-01), Cappelletti et al.
patent: 5627779 (1997-05-01), Odake et al.
patent: 5646886 (1997-07-01), Brahmbhatt

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