Source bias compensation for page mode read operation in a flash

Details Source bias compensation for page mode read operation in a flash Source bias compensation for page mode read operation in a flash

1999-10-19

2000-09-12

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518522, 36518511, 36518512, 365210, 3652385, G11C 1606

Patent

active

06118702&

ABSTRACT:
A page mode memory senses a large number of bits simultaneously. The associated read current creates a source bias in the core cells which alters the sense margin at the sense amplifier. To address this problem, a memory integrated circuit (100) includes an array (102) of core cells, each core cell having a ground node (220, 222, 224). A ground line (230) couples the ground node of each core cell to a ground potential (Vss) and establishes a variable parasitic potential between the ground node and Vss. For sensing the data state of the core cells, a reference core cell (252) matches the array core cells and has a reference ground node (262). A circuit element (256) is coupled between the reference ground node and Vss to establish a variable reference potential to match the variable parasitic potential.

REFERENCES:
patent: 5923590 (1999-08-01), Yero
patent: 5943286 (1999-08-01), Orita

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