Sorting networks having enhanced layout

Details Sorting networks having enhanced layout Sorting networks having enhanced layout

1997-07-08

2000-02-01

Olms, Douglas W.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370389, 370352, 370394, 370397, H04L 1228

Patent

active

060211318

ABSTRACT:
Sorting networks having enhanced layouts, and a method for developing such layouts, are disclosed. The improved layouts use 5/4 N grid rows, where N is the number of network inputs. Additionally, up to log (N) permutations of interconnections within the network are combined into a single permutation, thereby reducing grid column requirements for network implementation. The improved layout, as applied to Batcher's bitonic and odd-even networks results in respective upper bound grid-areas of 11.25N.sup.2 +o(N.sup.2) and 9.375N.sup.2 +o(N.sup.2) grid units for a network of N inputs.

REFERENCES:
patent: 5636210 (1997-06-01), Agrawal
C.D. Thompson, "The VLSI Complexity of Sorting," IEEE Trans. Computers, vol. C32, No. 12, pp. 1171-1184, Dec. 1983.
A Bitonic Sorting Network with Simpler Flip Interconnections, Dec. 14, 1996 .

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