Sorting/merging tree for determining a next tournament champion

Details Sorting/merging tree for determining a next tournament champion Sorting/merging tree for determining a next tournament champion

1990-10-18

1994-02-15

Lee, Thomas C.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

34082502, 3642821, 36422941, 364DIG1, 364974, 364DIG2, G06F 736, G06F 722

Patent

active

052874940

ABSTRACT:
A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provide input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered. By storing sorted keys (codewords) plus the address ID, reuse of codewords (in formation of longer strings, etc.) is made possible.

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