Boots – shoes – and leggings
Patent
1983-09-22
1985-12-17
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 724
Patent
active
045596123
ABSTRACT:
An integrated sorting device for data words comprises a bidirectional bus (54) to which are connected the address input (AD) of a memory (52), a command register (66) for memory clear, sorting criterion and pointer reset signals, a multiplexer (74) and an address counter (98). In a write mode of operation, data words arriving on the bus address the memory and representations thereof, e.g. binary 1s, are stored therein. Briefly before each such storage operation, the same memory location is read and any representation (DOUT) already stored therein is used to trigger flip-flop (82) to indicate that an overflow condition exists. During a read operation, the address counter addresses the successive memory addresses under the control of an oscillator (88). When a filled memory location is reached, a further flip-flop (94) causes the counter to stop and a "ready" signal (RDY) is outputted. The counter resumes counting when the relevant memory location has been read completely. The multiplexer feeds the overflow signal and a read termination signal derived from the address counter to the bus.
REFERENCES:
patent: 3587057 (1971-06-01), Armstrong
patent: 3713107 (1973-01-01), Barsamian
patent: 4031520 (1977-06-01), Rohner
Cannon, Jr. James J.
Haken Jack E.
U.S. Philips Corporation
Zache Raulfe B.
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