Sorting circuit using first and last buffer memories addressed b

Details Sorting circuit using first and last buffer memories addressed b Sorting circuit using first and last buffer memories addressed b

1989-11-13

1993-01-12

Lee, Thomas C.

Boots, shoes, and leggings

3642515, 3642594, 3649208, 3649426, 3649601, 3649623, 3642229, 364DIG1, 401462, 395425, G06F 734, G06F 1562

Patent

active

051797178

ABSTRACT:
A circuit for sorting a plurality of inputted (reference-axis) data includes an index generator for generating an index (datum number) for each of the inputted data; a first buffer memory having storage areas each of which can be addressed by the data, the first buffer memory for storing an index generated by the index generator when the corresponding data is initially inputted into the index generator; a last buffer memory having storage areas each of which can be addressed by the data, the last buffer memory for updating and storing an index generated by the index generator at each time when the corresponding data is inputted thereinto; a chain buffer memory having chain index storage areas each of which can be addressed by the previous index in the chain; a first control for writing a new updated index into a chain index storage area addressed by a before-updated index at each time when the index of the last buffer memory is updated; a second control for writing the index of the data into the chain datum number storage areas so that they will be chained with each other in the ascending or descending order of the sorted data; and a third control for reading the index in the chain index storage areas in accordance with a predetermined read-out rule index. Such an arrangement of the sorting circuit can sort and output a plurality of data in a simple and high-speed manner.

REFERENCES:
patent: 4443860 (1984-04-01), Vidalin
patent: 4570221 (1986-02-01), Martens
patent: 4679139 (1987-07-01), Durbin
patent: 4991134 (1991-02-01), Ivsin

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