Sonos-based non-volatile memory AND-array

Details Sonos-based non-volatile memory AND-array Sonos-based non-volatile memory AND-array

2011-05-31

2011-05-31

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185170, C365S185290

Reexamination Certificate

active

07952932

ABSTRACT:
Consistent with an example embodiment, a non-volatile memory cell on a semiconductor substrate includes a first and a second transistor. Each transistor is arranged a s a memory element that includes two diffusion regions capable of either acting as a source or drain, a charge storage element and a control gate element. A channel region is located intermediate the two diffusion regions. The charge storage element is located over the channel region and the control gate element is arranged on top of the charge storage element. One diffusion region of the first transistor and one diffusion region of the second transistor form a common diffusion region. The other diffusion region of the first transistor is connected as first diffusion region to a first bit line, the other diffusion region of the second transistor is connected as second diffusion region to a second bit line and the common diffusion region is connected to a sensing line.

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