Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2001-12-31
2002-11-19
Paladini, Albert W. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S634000, C257S635000, C257S636000, C257S640000, C257S649000, C257S650000
Reexamination Certificate
active
06483173
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of low dielectric constant layers for use in integrated circuits with particular reference to methods for preventing peeling and delamination of such films.
BACKGROUND OF THE INVENTION
The internal dimensions within integrated circuits continue to shrink, including the thicknesses of the dielectric layers used to separate various layers of wiring from one another. However, as these wiring levels are brought closer together, the possibility of cross-coupling between them starts to rise as well as the incidence of parasitic capacitances. One way to minimize this problem is to reduce the dielectric constants of these inter-metal layers. Thus there is considerable interest in developing low k materials as well as deposition methods for them that are compatible with integrated circuit technology.
For our purposes we will define a low k dielectric as one that has a dielectric constant close to or less than about 3. Several such materials are known to exist but they have the disadvantage that they are organic rather than inorganic compounds. Examples include hydrogen silsesquioxane, fluorinated polyimide, polyarylene ether, fluorinated arylene ether, polytetrafluoro-ethylene, and benzocyclobutene. Because of their organic nature these materials are innately soft, which physical property can give rise to problems during semiconductor processing, particularly during planarization, by chemical mechanical polishing (CMP).
The present invention is concerned with low dielectric constant materials that are inorganic in nature, such as spin-on glass (SOG), fluorinated silicon glass (FSG) and, particularly, methyl-doped porous silica which is referred to by practitioners of the art as black diamond, or BD. When formed as will be described below, about 36% of a BD layer's volume is in the form of pores having a diameter between about 8 and 24 Angstroms.
Dual damascene structures have received widespread application in recent years so it is important that processes for laying down low dielectric constant materials be compatible with such structures. An example of a dual damascene structure is schematically illustrated in FIG.
1
. See there is a substrate
11
over which two layers of dielectric material
14
and
15
have been deposited. Via hole
14
has been etched through lower dielectric layer
14
and trench
13
(long dimension running normal to the plane of the figure) has been etched through upper dielectric layer
15
. Via and trench were over-filled with metal (usually copper) and then the upper surface was planarized, as shown.
Inorganic low k dielectrics enjoy several advantages over the organic variety, such as good thermal conductivity suitability for production, but one problem associated with them is that many of them, when in thin film form, are found to be in a state of high tensile stress. This is the case, regardless of how they are deposited. Because of this, low k inorganic films have a tendency to delaminate, particularly near the edges of the substrate where the restoring forces are the strongest. This is illustrated in
FIG. 2
which shows silicon wafer
22
which has been coated with a layer of (for example) BD. For a 25 cm. wafer, an outer annular region
23
, whose width varies between about 0.5 and 2 cm has a tendency to come away. Aside from the yield loss in the affected area, the delaminated film is a source of particulate contamination and, most importantly, the wafer alignment mark (shown schematically in the figure as area
24
) can easily be obscured (blinded) by this.
A routine search of the prior art was performed but no references that teach the exact processes and structures of the present invention were discovered. Several references of interest were, however, encountered along the way. For example, in U.S. Pat. No. 6,025,280, Brady et al. show a low k oxide process using nitrous oxide and TEOS with an organic reactant. In U.S. Pat. No. 5,851,892, Lojek et al. show an oxidation process using a nitrogen pre-anneal. Reference to BD was found on the web-site for Applied Materials in the form of a press release dated Feb. 28, 2000 describing this material.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for depositing a layer of low dielectric constant material on a substrate without subsequent delamination of said layer.
Another object of the invention has been to provide a process for depositing a layer of black diamond on a silicon wafer without subsequent delamination of said layer.
A further object of the invention has been to provide a dual damascene structure in which the dielectric is black diamond.
A still further object has been to provide a process for forming said dual damascene structure.
These objects have been achieved by inserting a layer of silicon nitride between the low k layer and the substrate. A key requirement is that said layer of silicon nitride be under substantial compressive stress (at least 5×10
9
dynes/cm
2
). In the case of a layer of black diamond, on which material the invention is particularly focused, a nucleating layer is inserted between the silicon nitride and the black diamond. A process for laying down the required layers is described along with an example-of applying the invention to a dual damascene structure.
REFERENCES:
patent: 5541445 (1996-07-01), Quellet
patent: 6232658 (2001-05-01), Catabay et al.
Jang Syun-Ming
Jeng Shwangming
Li Lain-Jong
Ackerman Stephen B.
Paladini Albert W.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Zarneke David A.
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