Solid via layer to layer interconnect

Details Solid via layer to layer interconnect Solid via layer to layer interconnect

2001-05-29

2003-01-07

Paladini, Albert W. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C361S780000, C257S691000

Reexamination Certificate

active

06504111

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and structure for providing an interconnect between layers of a multilayer circuit board.
2. Related Art
Typically, high density multilayer circuit boards are constructed of several layers joined by dielectric material to form a stack. Each layer may include an electrically conductive element, such as, a signal plane or a power plane. Layer to layer interconnections may be accomplished using vias, which are typically formed by drilling a hole through layers, followed by plating the wall of the hole with an electrically conductive material. The electrically conductive material along the wall of the via interconnects the conductive elements in the layers.
SUMMARY OF THE INVENTION
A first general aspect of the present invention provides a structure comprising:
a stack comprising an at least one layer;
a via opening extending through the at least one layer of the stack; and
wherein the via opening is filled with a solid conductive plug.
A second general aspect of the present invention provides a method comprising:
providing an at least one layer;
forming a via opening in the at least one layer; and
filling the via opening with a solid conductive plug.
A third general aspect of the present invention provides a method comprising:
forming a plurality of layers;
forming at least one via opening extending through at least one layer; and
filling the at least one via opening with a solid conductive plug.


REFERENCES:
patent: 4328531 (1982-05-01), Nagashima et al.
patent: 4967314 (1990-10-01), Higgins, III
patent: 5191174 (1993-03-01), Chang et al.
patent: 5309629 (1994-05-01), Traskos et al.
patent: 5363280 (1994-11-01), Chobot et al.
patent: 5444189 (1995-08-01), Nakaso et al.
patent: 5545429 (1996-08-01), Booth et al.
patent: 5576519 (1996-11-01), Swamy
patent: 5699613 (1997-12-01), Chong et al.
patent: 5729897 (1998-03-01), Schmidt et al.
patent: 5734560 (1998-03-01), Kamperman et al.
patent: 5768108 (1998-06-01), Miura et al.
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 6013876 (2000-01-01), Caporizzo
patent: 6023029 (2000-02-01), Armezzani et al.
patent: 6106891 (2000-08-01), Kulesza et al.
patent: 6234067 (2001-11-01), Nishiyama
patent: 6323439 (2001-11-01), Kambe et al.
patent: 0 955 795 (1999-11-01), None
Multilayer Substrate with Low Coefficient of Thermal Expansion, Nakamura et al., 2000 International Symposium on Microelect, pp. 235-240.

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