Solid state time delay and holding circuit

Details Solid state time delay and holding circuit Solid state time delay and holding circuit

1975-11-24

1977-03-01

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307252B, 307246, 328129, H03K 513, H03K 1760

Patent

active

040103897

ABSTRACT:
Circuitry operating as a time delay/holding relay whereby a connection is established between a pair of output terminals whenever power is applied between input terminals and for a timed period after the receipt of a predetermined signal. A first integrated circuit is connected as a free running multivibrator to generate a pulse train for maintaining a bilateral thyristor in its conductive state to close the connection. A second integrated circuit, identical to the first, is utilized to enable the first integrated circuit. The second integrated circuit is connected as a free running multivibrator but oscillations are disabled until the receipt of the predetermined signal. This maintains the enabling signal for the specified time period after the signal is received. External connections of components to the second integrated circuit changes the internal operation of that circuit.

REFERENCES:
patent: 3597637 (1971-08-01), Vandemore et al.
patent: 3745382 (1973-07-01), Hoge et al.
patent: 3846648 (1974-11-01), Scott
patent: 3873853 (1975-03-01), Ahmed
patent: 3950657 (1976-04-01), Sheng et al.

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