1992-05-28
1994-06-14
Beausoliel, Jr., Robert W.
Excavating
395425, 371 102, 371 103, 3649646, 3649647, G06F 1100
Patent
active
053216970
ABSTRACT:
An improved solid state storage device (SSD) with memory organized into a plurality of groups, each group including a plurality of ranks, and each rank having at least two banks sharing a bidirectional data bus. A matrix reorder circuit is used to distribute data across individual memory components in a way that prevents multibit uncorrectable or undetectable errors due to the failure of a single memory component. The matrix reorder circuit is used for both reading and writing data, and operates on a stream of pipelined data of arbitrary length.
According to another aspect of this invention, a flaw map and additional hot spare memory are used to electrically replace failing memory components in the
According to another aspect of this invention, memory in a bank is accessed during one half of a reference cycle and refreshed during the second half of the reference cycle, each bank being 180 degrees out of phase with the other so that a read or write is performed on one bank while a memory refresh is performed on the other bank.
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Patent Abstracts of Japan, vol. 010, No. 170 (E-412); Jun. 17, 1986 & JP,A,61 020 435 (Nippon Denshin Denwa Kosha) Jan. 29, 1986.
Anderson Michael L.
Fromm Eric C.
Heidtke Lonnie R.
Beausoliel, Jr. Robert W.
Cray Research Inc.
Kluth Daniel J.
Tu Trinh
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