Solid state memory system including plural memory chips and a se

Details Solid state memory system including plural memory chips and a se Solid state memory system including plural memory chips and a se

1991-07-26

1995-07-04

Gossage, Glenn

Static information storage and retrieval

Magnetic bubbles

Guide structure

395325, 395500, 365900, 365 52, 36523003, 364DIG1, G06F 1200, G06F 1300, G11C 504, G11C 1606

Patent

active

054308593

ABSTRACT:
A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit and assigned an array address. A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A particular multi-bit mount configuration is used to unconditionally select the device mounted thereon. A predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

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