Solid state interconnection system for three dimensional integra

Details Solid state interconnection system for three dimensional integra Solid state interconnection system for three dimensional integra

1982-06-03

1988-06-28

James, Andrew J.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

357 49, 357 55, 357 56, 357 82, 357 67, 357 40, 324158P, H01L 2350, H01L 2908, H01L 2514, H01L 2952

Patent

active

047543167

ABSTRACT:
A semiconductor circuit apparatus including several semiconductor substrates interconnected by having elevated portions of one substrate contacting the surface of the second substrate where both substrates include at least one electrical circuit. Also included is a method for forming this three dimensional integrated circuit structure by forming the elevated portions of the semiconductor substrate by applying an orientation-dependent etch and then applying an electrically conductive coating to this elevated portion. Electrically conductive bonding pads are formed on the second semiconductor substrate. These pads are selectively positioned relative to the elevated portions formed on the first semiconductor substrate. Contacts between the first and second substrate are formed by forming bonds between the elevated portions on the one substrate and the electrically conductive pads on the second substrate.

REFERENCES:
patent: 3748548 (1973-07-01), Haisty et al.
patent: 3887404 (1975-06-01), Chane
patent: 3895359 (1975-07-01), Knoll et al.
patent: 4275410 (1981-06-01), Grinberg et al.
patent: 4400868 (1983-08-01), Antypas et al.
"Stacked High-Density Multichip Module", Jarvela et al., IBM Tech. Disclosure Bull., vol. 14, No. 10, Mar. 1972, pp. 2896-2897.

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