Solid-state inductor and method for same

Details Solid-state inductor and method for same Solid-state inductor and method for same

2002-04-22

2003-11-25

Mai, Anh (Department: 1773)

Dynamic magnetic information storage or retrieval

Head

Magnetoresistive reproducing head

C360S324200

Reexamination Certificate

active

06654210

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor fabrication and, more particularly, to a solid-state inductor for analog integrated circuit (IC) fabrication and a method for processing the same.
2. Description of the Related Art
Conventionally, an IC integrated inductor is formed from a metal line, designed in spiral form, overlying a thick layer of insulator on silicon substrate. The inductance value of an inductor so formed is very low, so that the formation of a practical inductor requires a large silicon area. Besides using a great amount of valuable IC area, the large-sized inductors generate parasitic reactances and unintended mutual inductances with components that are adjacent, overlying, or underlying the inductor.
Further, a conventional inductor is a passive component, meaning that once it is formed in the IC, the inductance value cannot be changed. Thus, the inductor cannot be used for frequency tuning. Frequency tuning would be desirable in the fabrication of circuits such as filters, antennas, and oscillators, to name a few of examples.
It would be advantageous if an IC inductor could be made smaller, with a greater inductance value.
It would be advantageous if the inductance value of an IC inductor could be varied or tuned in an IC circuit.
SUMMARY OF THE INVENTION
The present invention describes a solid-state inductor, which has a relatively high inductance value, requires a very small area, and is suitable to be integrated into the conventional integrated circuits, whether it is a CMOS or a Bipolar circuit fabricated on silicon, or on compound semiconductor substrate.
Accordingly, a method is provided for forming a solid-state inductor. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; applying an electrical field treatment to the CMR thin film in the range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in the range of 100 nanoseconds to 1 millisecond; in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; and, in response to the applied bias voltage, creating an inductance between the top and bottom electrodes. When the applied bias voltage is varied, the inductance varies in response.
The CMR thin film overlying the bottom electrode includes using a material such as Pr
0.3
Ca
0.7
MnO
3
(PCMO), La
0.7
Ca
0.3
MnO
3
(LCMO), Y
1−x
Ca
x
MnO
3
(YCMO), or high-temperature super conductor (HTSC) materials with a film thickness of approximately 2000 Å. Forming the CMR thin film overlying the bottom electrode includes: spin-coating a first layer having a thickness of approximately 670 Å; annealing the first layer at a temperature of approximately 650 degrees C. for a period of approximately 30 minutes; spin-coating a second layer, having a thickness of approximately 670 Å, overlying the first layer; annealing the second layer at a temperature of approximately 550 degrees C for a period of approximately 30 minutes; spin-coating a third layer, having a thickness of approximately 670 Å, overlying the second layer; and, annealing the third layer at a temperature of approximately 550 degrees C for a period of approximately 30 minutes.
Additional details of the above-described method, and a solid-state inductor device are presented below.


REFERENCES:
patent: 6204139 (2001-03-01), Liu et al.
patent: 6225801 (2001-05-01), Jin et al.
patent: 6316131 (2001-11-01), Saboungi et al.
patent: 6495828 (2002-12-01), Tidrow et al.

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