Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-07-06
2003-12-02
Porta, David (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S302000
Reexamination Certificate
active
06657177
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-205422, filed Jul. 6, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state imaging system using a solid-state imaging device and, more specifically, to a solid-state imaging system using a solid-state imaging device of an amplification type provided with a charge detecting circuit for each pixel or cell, which may be used in video cameras and electronic still cameras.
2. Description of the Related Art
Solid-state imaging devices include CCD (charge coupled device)-based solid-state imaging devices and amplification type solid-state imaging devices provided with a charge detecting device for each pixel. To increase the dynamic range, two main approaches have been adopted: one is to allow the photoelectric conversion characteristic to have nonlinearity, and the other is to use an operation of setting the integration time to be less than the frame rate (the time required to read out one frame), i.e., to employ the so-called electronic shutter function.
With conventional CCD solid-stage imaging devices, an electronic shutter operation using vertical overflow drains is often performed for improving the pixel aperture ratio. In such an electronic shutter operation, much structural difficulties are involved in setting different integration times to each pixel on the imaging surface; therefore, all the pixels are often allocated the same integration time. Thus, the integration time will be set so that the brightest pixel will not be saturated. In that case, an output of a pixel on which dim light falls will be buried in noise components because of its insufficient integration time, causing a problem that a sufficient signal-to-noise ratio in the entire image cannot necessarily be obtained.
In contrast, in the amplification type solid-state image device, unlike the CCD solid-stage imaging devices, the charge transfer operation is performed only in the periphery of photodiodes; thus, the power and voltage required of the charge transfer operation become unnecessary and they are suited for use in mobiles which are operated from batteries.
FIGS. 8A and 8B
show a schematic arrangement of a conventional amplification type solid-state imaging device. In this exemplary arrangement, one photodiode forms one unit cell.
In
FIGS. 8A and 8B
, Sj denote vertical signal lines, Ij, current sources, SHj, shift gates, CAj and CBj, capacitances for signal processing, CLPj, clamping gates for removing offset, Hj, line readout gates, LHj, line readout pulse lines, &phgr;Hj, line readout pulses, LADi, address pulse lines, &phgr;ADi, address pulses, LRi, readout pulse lines, &phgr;Ri, readout pulses, LRSi, reset pulse lines, &phgr;RSi, reset pulses, LSH, a shift pulse line, &phgr;SH, a shift pulse, LCLP, a clamp pulse line, &phgr;CLP, a clamp pulse, LCR, a clear pulse line, and &phgr;CR, a clear pulse.
In addition,
20
denotes a pulse generator that generates the pulses &phgr;Di, &phgr;Ri, and &phgr;RSi;
21
, a pulse generator that generates the pulses &phgr;SH and &phgr;CLP;
23
, a clamping DC power supply;
24
, a horizontal signal line;
25
, a capacitor attached to the horizontal signal line
24
;
26
, an output buffer circuit that detects the potential on the horizontal signal line and outputs the detected potential with impedance conversion;
27
, an output node;
28
, a gate for resetting the potential at the capacitor
25
; and
29
, a power supply for generating a potential at the reset time. The output voltage of the power supply
29
(assumed to be Vb) is set with the characteristic of the output buffer circuit
26
taken into account. A clear pulse &phgr;CR is applied to the gate
28
before each of the line readout pulses &phgr;Hj is applied to a corresponding one of the line readout gates Hj with the result that the capacitor
25
is fixed at Vb.
The horizontal pulse generator
22
generates the pulses &phgr;Hj and &phgr;CR so that the imaging device is driven to perform a normal horizontal line read operation within each horizontal line period, as shown in FIG.
9
.
In the imaging area on the semiconductor substrate, unit cells Pij are two-dimensionally arrayed in m columns and n rows, the subscript i being the row number from 1 to m and j being the column number from 1 to n. For each row of the unit cells, an address pulse line LADi, a readout pulse line Lri and a reset pulse line LRSi are provided in the horizontal direction. Each unit cell Pij is connected to a pulse generator
20
as vertical driving means to receive an address pulse &phgr;ADi, a readout pulse &phgr;Ri, and a reset pulse &phgr;Rsi over the three pulse lines (the address pulse line LADi, the readout pulse line Lri, and the reset pulse line LRSi). For each column of the unit cells Pij, a vertical signal line Sj is provided in the vertical direction. Each unit cell Pij has its output line
8
connected to a corresponding one of the vertical signal lines Sj.
As previously described, the horizontal pulse generator
22
generates the pulses &phgr;Hj and &phgr;CR so that the imaging device is driven to perform a normal horizontal line read operation within each horizontal line period, as shown in FIG.
9
.
FIG. 9
illustrates the conventional timing of pulse signals for driving the solid-state imaging device of
FIGS. 8A and 8B
using a system of non-interlaced scanning.
In this diagram, HBLK denotes a horizontal sync pulse signal the high-level interval of which indicates the horizontal line blanking period. The interval when HBLK is low is the line effective scanning period, during which line readout pulses &phgr;Hj are produced. The line blanking period and the line effective scanning period form one line scanning period (
1
H). In the line scanning period, a signal is read from each unit cell during the line blanking period and stored in the form of charge at the corresponding capacitor CBj. After that, the line readout transistors Hj are turned on in sequence to connect capacitors
25
and CAj, CBj in parallel to read the stored signal charges.
Next, the read operation of the unit cells Pij will be described in detail with reference to the timing diagram shown in FIG.
9
.
Charges produced as a result of photoelectric conversion of light incident on the photodiode
1
are stored in it until the readout transistor
2
is turned on. In the line blanking period, first, at time t=t
0
, the address pulse &phgr;ADi is set high to turn the address transistor
6
on, thus forming a source follower circuit from the vertical signal line Sj, the current source Ij, and the potential detecting transistor
5
so as to allow the transistor
5
to detect charges at the storage node
3
. Thereby, only the potential determined by the gate potential of the transistor
5
corresponding to the amount of charge at the storage node
3
is transferred to the vertical signal line Sj.
At the beginning of the line blanking period, the reset pulse &phgr;Rsi is set high to turn the reset transistor
4
on, which allows the amount of charge resulting from integration of dark current at the storage node
3
to be drained away at the beginning of the line blanking period. Thereby, the storage node
3
is set at the supply voltage (Vdd).
When the amount of charge Qij has been transferred from the photodiode
1
to the storage node
3
, the potential V
3
ij
at the storage node is given by
V
3
ij=Vdd+Qij/Cij
(1)
where Cij is capacitance associated with the storage node and Vdd is the supply voltage.
The potential V
3
ij
is detected by the potential detecting transistor
5
, so that the potential V
8
ij
on the output line
8
becomes
V
8
ij=mV
3
ij+Voij
=
m
(
Vdd+Qij/Cij
)+
Voij
=
mQij/Cij+mVdd+Voij
(2)
where m is the modulation factor of the transistor (gate)
5
and Voij is the offs
Kabushiki Kaisha Toshiba
Lee Patrick J.
Porta David
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