Solid state imaging sensor in a submicron technology and...

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation

Reexamination Certificate

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C257S427000

Reexamination Certificate

active

06656760

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the field of solid state imaging devices and to a method of manufacturing and operating of such devices. More in particular a solid state imaging device manufacturable in a Metal-Oxide-Semiconductor (MOS) or in a Complementary Metal-Oxide-Semiconductor (CMOS) technology is disclosed.
BACKGROUND OF THE INVENTION
Solid state imaging sensors are known in the art. Commonly solid state imaging sensors are implemented in a CCD-technology or in a CMOS- or MOS-technology. Solid state imaging sensors find a widespread use in camera systems. In this embodiment a matrix of pixels comprising light sensitive elements constitutes an imaging sensor, which is mounting in the camera system. The signal of said matrix is measured and multiplexed to a so-called video-signal.
Solid state imaging sensor based camera systems in general dominate electronic imaging applications such as Closed Circuit Television (CCTV), video cameras and camcorders, scanners and newly developed markets such as PC (Personal Computer)-cameras, PDA's, cell phones and DSC, and cameras for video conferencing and Digital Still Cameras. Yet another application of solid state imaging sensors in camera systems is the use in digital photography camera systems wherein the actual image is taken within the solid state sensor instead of on a film material. One popular form of solid state image sensor is the Charge Coupled Device (CCD) image sensor, while sensors built entirely in standard CMOS technology are also becoming used. Such CCD and CMOS image sensors commonly comprise an array of pixels formed in a semiconductor substrate, each pixel comprising a photosensitive element which is normally in the form of a photodiode, or alternatively a polysilicon electrode (photogate), for responding to incident light.
CCD-based camera systems have less noise fluctuations in the image compared to CMOS- or MOS-based camera systems. Therefore CCD-based camera systems are nowadays preferred in applications wherein a high image quality is required such as video or still camera applications. There is an ongoing effort in the art to improve the image quality of CMOS-based camera systems. Due to the further miniaturization of the CMOS electronics technology, it is furthermore possible to realize complex CMOS- or MOS-based pixels as small as CCD-based pixels. It is a further advantage of CMOs- or MOS-based pixels that CMOS is a technology being offered by most foundries whereas CCD-technology is rarely offered and a more complex and expensive one. Of the image sensors implemented in a CMOS- or MOS-technology, CMOS or MOS image sensors with passive pixels and CMOS or MOS image sensors with active pixels are distinguished. An active pixel is configured with means integrated in the pixel to amplify the charge that is collected on the light sensitive element. Passive pixels do not have said means and require a charge-sensitive amplifier that is not integrated in the pixel and is connected with a long line towards the pixel. For this reason, active pixel image sensors are potentially less sensitive to noise fluctuations than passive pixels. Due to the additional electronics in the active pixel, an active pixel image sensor may be equipped to execute more sophisticated functions, which can be advantageous for the performance of the camera system. Said functions can include filtering, operation at higher speed or operation in more extreme illumination conditions.
The manufacturing of CMOS based active pixel sensors (APS) has several more advantages. The APS sensors can easily be miniaturized. This is because the camera system basically can be a single chip and a lens, with the single chip containing signal processing functionality. The possibility that is offered for miniaturizing the whole camera system is important e.g. for portable applications such as cell phones or portable PC's. Due to the increased integration of functionality on one chip, also the power consumption of the APS chip can be reduced. Furthermore, the integration of signal processing functions on chip allows for the implementation of specific features such as random access to each pixel of the sensor, and readout of small windows of interest for applications such as machine vision or tracking, and electronic pan and zoom for consumer applications.
As stated above, CMOS image sensors with active pixels include in each pixel at least a photosensitive element and at least one MOS amplifying transistor. A common pixel type is the so-called 3T-pixel that includes a photosensitive element, a reset transistor in series with the photosensitive element and an amplifying transistor connected to the photosensitive element and the reset transistor (see e.g. O. Yadid-Pecht, IEEE Trans. Electr. Dev. 38(8), 1772 (1991)). In some applications, the reset transistor is configured so as to define a 3T-transistor with a logarithmic characteristic (see e.g. M. A. mahowald, SPIE Proceedings Vol. 1473, 52 (1991)).
The imaging process in solid state imaging devices is initiated by radiation impinging on the solid state substrate. In a silicon substrate the impinging electromagnetic radiation such as light creates charge carriers (electron-hole pairs) that are to be collected and further processed in the amplifying electronics in the periphery of the matrix of pixels and/or in the amplifying electronics integrated in the pixel or the matrix of pixels. Commonly the impinging light is detected in photosensitive elements wherein a p-n or n-p or a n
+
-p or p
+
-n or any such junction, in the sequel labeled as p-n junction, is present. Thus the photosensitive element can also be a transistor such as a bipolar transistor, or the photosensitive element can also be part of a transistor such as an unsilicided drain/source area of a MOS transistor. The photosensitive element can also be a photogate such as a one-cell charge coupled device (CCD) line or even an IR type of sensor. The p-n junction commonly is in reverse bias, thus with an enhanced depletion layer. The p-n junctions are commonly located at the surface of the solid state substrate wherein the matrix of pixels is integrated. Examples of the geometry of such devices is shown in
FIG. 2
of the patent application WO93/19489 and in
FIGS. 3-11
of the patent application WO98/49729. A common geometry is schematically shown in
FIG. 1
of the present patent application. Shown in
FIG. 1
is the cross section of part of a solid state imaging device as commonly implemented in a MOS-technology. The photosensitive element is formed by a n
+
-p junction (n
+
-region (
11
) on p-region (
12
)) of which the depletion region (
13
) can be enhanced through the application of an appropriate voltage. The p-region can be a p-well in a substrate or can be the p-type substrate itself. The different photosensitive elements are separated by field isolation regions (LOCOS regions made of oxide material (
14
)). Also a whole pixel configuration, i.e. the associated amplifying and/or access transistors, can be integrated with the photosensitive elements in the regions in-between the isolation regions.
For the majority of applications of solid state imaging devices, the achievement of a high efficiency in the conversion of the impinging radiation is an important aim and an important design criterion. In particular, for CMOS based imaging devices it is advantageous that this aim is realized without changing significantly the MOS process flow as such non-standard processing would lead to an important price increase of the imaging devices.
Patent application EP883187 discloses a CMOS based imaging device having a high efficiency in the conversion of the impinging radiation. The concept as disclosed in EP883187 however is suitable only for larger gate length devices, namely CMOS based imaging devices implemented in a 1.2 or 0.7 or 0.5 or 0.35 &mgr;m CMOS technology. The concept furthermore requests some changes to a standard CMOS process flow. The concept of EP883187 still shows an imperfection in

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