Solid-state imaging device, method of driving solid-state...

Details Solid-state imaging device, method of driving solid-state... Solid-state imaging device, method of driving solid-state...

1997-08-21

2001-03-06

Garber, Wendy (Department: 2712)

Television

Camera, system and detail

With single image scanning device supplying plural color...

Reexamination Certificate

active

06198507

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device which includes a charge transfer unit comprising a CCD, for example, for producing an image output signal based on all-pixel reading principles or noninterlaced principles, the solid-state imaging device being capable of selectively producing an output image signal based on noninterlaced principles, a method of driving the solid-state imaging device for such a charge transfer process, a camera device incorporating the solid-state imaging device, and a camera system for storing an image signal based on the noninterlaced principles (hereinafter referred to as a “noninterlaced signal”) from the camera device into an external memory and displaying a noninterlaced signal from the camera device on a monitor screen.
Generally, camera devices for imaging and displaying subjects on monitor devices have solid-state imaging devices for producing an output image signal based on interlaced principles because the monitor devices usually employ interlaced principles such as NTSC or the like.
The solid-state imaging devices for producing an interlaced output image signal generally include a CCD image sensor of the vertical four-phase drive, IT (interline transfer) type and a CCD image sensor of the vertical four-phase drive, FIT (frame interline transfer) type.
As shown in
FIG. 1
of the accompanying drawings, an CCD image sensor of the interline transfer type has an imaging unit
103
comprising a matrix of photodetectors
101
for photoelectrically converting incident light into electric charges depending on the amount of the incident light and a number of vertical shift registers
102
shared by columns of photodetectors
101
and arranged along rows of photodetectors
101
.
The image sensor also has a horizontal shift register
104
shared by the vertical shift registers
102
. The horizontal shift register
104
has a final stage connected to an output unit
105
which has a charge-to-voltage converter comprising a floating-diffusion device or a floating-gate device and an output amplifier for amplifying an output signal from the charge-to-voltage converter.
When vertical transfer pulses &phgr;V
1
~&phgr;V
4
in four phases are supplied to the imaging unit
103
, a distribution of potentials under respective vertical transfer electrodes of the imaging unit
103
varies successively to transfer signal charges along the vertical shift registers
102
in a vertical direction (to the horizontal shift register
104
).
When horizontal transfer pulses &phgr;H
1
, &phgr;H
2
in two different phases are then applied to horizontal transfer electrodes in the form of two polycrystalline silicon layers, for example, on the horizontal shift register
104
, the signal charges are successively transferred to the output unit
105
. The output unit
105
converts the transferred signal charges into an electric signal, which is then outputted as an image signal S from an output terminal fout.
In an odd-numbered field, first and second lines and third and fourth lines are mixed with each other in the vertical shift registers
102
, and transferred to the horizontal shift register
104
. In an even-numbered field, second and third lines and fourth and fifth lines are mixed with each other in the vertical shift registers
102
, and transferred to the horizontal shift register
104
.
Recently, there has been a growing demand for an all-pixel reading CCD image sensor for independently reading information of all pixels and a CCD image sensor for noninterlacing pixel signals on the frame transfer principles, for use in applications such as the inputting of images to computers and electronic still cameras.
One proposed image sensor for reading all pixels has a vertical transfer unit comprising a 3-layer, 3-phase CCD as shown in
FIG. 2
of the accompanying drawings. Those parts shown in
FIG. 2
which are identical to those shown in
FIG. 1
are denoted by identical reference numerals, and will not be described below.
A process of vertically transferring signal charges along the vertical shift registers
102
in the 3-layer, 3-phase CCD image sensor will be described below with reference to a timing chart shown in
FIG. 3
of the accompanying drawings and an operation diagram shown in
FIG. 4
of the accompanying drawings.
After the end of a cycle of reading signal charges in a vertical blanking period, a signal charge “e” is transferred to and stored in a potential well formed beneath a second vertical transfer electrode
111
b
at a time t1. At a next time t2, since a first vertical transfer pulse &phgr;V
1
is of a high level, a potential well is formed beneath a first vertical transfer electrode
111
a
. The signal charge “e” after it is read is transferred to and stored in the potential wells that are consecutively formed beneath the first and second vertical transfer electrodes
111
a
,
111
b.
At a next time t3, since a second vertical transfer pulse &phgr;V
2
is of a low level, a potential barrier is formed beneath the second vertical transfer electrode
111
b
. The signal charge “e” is transferred to and stored in the potential well that is formed beneath the first vertical transfer electrode
111
a.
At a next time t4, since a third vertical transfer pulse &phgr;V
3
is of a high level, a potential well is formed beneath a third vertical transfer electrode
111
c
. The signal charge “e” is transferred to and stored in the potential wells that are consecutively formed beneath the first and third vertical transfer electrodes
111
a
,
111
c.
At a next time t5, since the first vertical transfer pulse &phgr;V
1
is of a low level, a potential barrier is formed beneath the first vertical transfer electrode
111
a
. The signal charge “e” is transferred to and stored in the potential well that is formed beneath the third vertical transfer electrode
111
c.
At a next time t6, since the second vertical transfer pulse &phgr;V
2
is of a high level, a potential well is formed beneath the second vertical transfer electrode
111
b
. The signal charge “e” is transferred to and stored in the potential wells that are consecutively formed beneath the second and third vertical transfer electrodes
111
b
,
111
c.
At a next time t7, since the third vertical transfer pulse &phgr;V
3
is of a low level, a potential barrier is formed beneath the third vertical transfer electrode
111
c
. The signal charge “e” is transferred to and stored in the potential well that is formed beneath the second vertical transfer electrode
111
b.
At this time, the signal charge “e” that has been stored in the second vertical transfer electrode
111
b
in the previous stage is transferred to the second vertical transfer electrode
111
b
in the next stage. In this manner, the first through third vertical transfer pulses &phgr;V
1
~&phgr;V
3
are applied respectively to the vertical transfer electrodes
11
a
~
111
c
, independently transferring the signal charges “e” of all the pixels successively in the vertical direction.
In the above electronic still camera, imaged information is displayed on a monitor device to determine an image angle.
Since a solid-state imaging device for use in an electronic still camera comprises an all-pixel reading CCD image sensor independently reading information of all pixels or a CCD image sensor for noninterlacing pixel signals based on the frame transfer principles, as described above, a monitor device for use with such a solid-state imaging device should preferably be of a noninterlaced type.
However, the noninterlaced monitor device is so expensive that it forms a bottleneck in presenting electronic still cameras for widespread usage.
For displaying noninterlaced imaged information on an inexpensive interlaced monitor device such as an NTSC monitor device, it is necessary to convert the noninterlaced signal to an interlaced signal.
To obtain an interlaced signal directly from a solid-state imaging device, it has been customary to mix signal charges from vertically adjacent two pixels in a vertical shift register. T

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