Solid-state imaging device having partially covered...

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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C348S316000

Reexamination Certificate

active

06222586

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a progressive-scan CCD solid-state imaging device, a method for producing the same, and a method for driving the same.
2. Description of the Related Art
Recently, CCD solid-state imaging devices have been widely used in multimedia-related devices such as electronic still cameras and image input devices for personal computers as well as video cameras. A conventional CCD solid-state imaging device for a video camera employs a field integration mode system in order to obtain a video signal conforming to 2:1 interlaced scanning used for the TV broadcasting system. According to the field integration mode system, signal charges in two adjacent vertical lines are mixed together, and a combination of the two vertical lines is switched between a first field and a second field.
A progressive-scan CCD solid-state imaging device reads signal charges in two vertical lines independently without mixing the charges thereof, and thus can realize both a high resolution of moving pictures and a high vertical resolution. Moreover, a progressive-scan CCD solid-state imaging device employs a non-interlaced scanning system with no 2:1 interlaced scanning. An image obtained by such an imaging device is relatively easily converted into an image used in personal computers.
In order to realize the progressive-scan system, it is required to form a vertical transfer CCD region for transferring one bit of data within a vertical pixel pitch (Lv) and then transfer and output a signal charge read from a photoelectric conversion region in a unit pixel area without being mixed with any signal charges read from any adjacent unit pixel areas.
For an imaging section of such a progressive-scan CCD solid-state imaging device, three structures described below, for example, have been proposed.
(1) The vertical transfer CCD region has a two-layer gate structure driven by a two-phase driving system (
FIGS. 9A
,
10
A and
11
A).
(2) The vertical transfer CCD region has a three-layer gate structure driven by a three-phase driving system (
FIGS. 9B
,
10
B and
11
B).
(3) The vertical transfer CCD region has a three-layer gate structure driven by a four-phase driving system (
FIGS. 9C
,
10
C and
11
C).
FIGS. 9A
,
9
B and
9
C are each structural views of a part of the imaging section corresponding to two pixel areas of the CCD solid-state imaging device having the respective structure described above.
FIGS. 10A
,
10
B and
10
C are each cross-sectional views of a lead part of the vertical transfer electrode in each pixel area wherein the lead part is provided.
FIGS. 11A
,
11
B and
11
C are diagrams illustrating a potential profile in the vertical transfer CCD region of the pixel areas respectively shown in
FIGS. 9A
,
9
B and
9
C, obtained when the charges are transferred. In
FIGS. 9A
,
9
B,
9
C,
10
A,
10
B,
10
C,
11
A,
11
B and
11
C, symbols &phgr;
v1
, &phgr;
v2
, &phgr;
v3
and &phgr;
v4
represent vertical transfer electrodes. Reference numeral
31
represents a p-well layer, reference numerals
32
a
and
32
b
each represent a photoelectric conversion region, and reference numeral
33
represents a vertical transfer CCD region. Reference numeral
34
represents a lead part of a vertical transfer electrode provided. Reference numeral
35
represents a potential barrier for determining the transfer direction, and reference numeral
36
represents a signal charge. Symbol Lv represents a vertical pixel pitch of a unit pixel area.
T. Okutani et al., “A ⅓-inch 330k Square-Pixel Progressive-Scan IT-CCD Image Sensor”, ITE'95: 1995 ITE Annual Convention, pp. 93 and 94 discloses the structure shown in
FIGS. 9B and 10B
of the three-phase driving system and the structure shown in
FIGS. 9C and 10C
of the four-phase driving system. In addition, K. Nanashima et al., “A ½-inch 330K Progressive-Scan CCD Image Sensor with Square-Pixel”, ITE Technical Report Vol. 18, No. 67, pp. 7-12 discloses a CCD imaging device of a three-phase driving system.
The conventional progressive-scan CCD solid-state imaging devices having the above-described structures, in which a part of a vertical transfer CCD region
33
which is included in one pixel area corresponds to one bit, have the following problems.
According to the structure shown in
FIGS. 9A and 10A
, a progressive scan is performed with the two-layer gate structure. A signal charge storage area and a potential barrier
35
for separating the charges are both formed below one electrode. In such a system, the potential barrier
35
cannot be formed in a self-aligned manner.
In the case where the potential barrier
35
is located below another vertical transfer electrode, a barrier or a dip is formed which impedes vertical transfer and tends to cause a charge transfer error. Moreover, as shown in
FIG. 11A
, the length of the signal charge storage area for each pixel area is shorter than Lv/2 by the length of the potential barrier
35
for separating the signal charges provided in the vertical transfer CCD region
33
.
According to the structure shown in
FIGS. 9B and 10B
, in which the vertical transfer CCD region
33
has a three-layer structure, a clock pulse is applied to each of the vertical transfer electrodes &phgr;
v1
, &phgr;
v2
and &phgr;
v3
in the respective layers (referred to as the “vertical three-phase driving system”). Such a three-layer gate structure has the drawbacks of a longer and more complicated production process compared to the two-layer structure and an excessively large stepped part on the surface of the pixel section as is apparent from
FIG. 10
, which shows a vertical cross-sectional view of the photoelectric conversion regions
32
a
and
32
b
. Moreover, as shown in
FIG. 11B
, the length of the area where signal charges can be stored for each pixel area is as short as Lv/3.
According to the structure shown in
FIGS. 9C and 10C
, the four-phase driving system is employed with a three-layer gate structure. Charges can be stored in two out of four phases, and thus the length of the signal charge storage area can be Lv/2 as shown in FIG.
11
C. However, this structure also has the drawbacks of a long and complicated production process and an excessively large stepped part on the surface of the pixel section. Such an excessively large stepped part on the surface is disadvantageous for size reduction of the CCD solid-state imaging device. Specifically, when a microlens is formed to improve the sensitivity, such a large stepped part makes it more difficult to smooth the surface.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a solid-state imaging device has a progressive-scan structure and includes, in a unit pixel area of a semiconductor substrate, a photoelectric conversion region and a vertical transfer CCD region for reading and transferring a signal charge stored in the photoelectric conversion region by performing four-phase driving using two vertical transfer electrodes each having a two-layer structure formed over the semiconductor substrate with a gate insulation layer disposed therebetween. Among the two vertical transfer electrodes each having a two-layer structure, lead parts of one vertical transfer electrode having the two-layer structure are positioned on the photoelectric conversion region in the unit area.
By such a structure, first through fourth electrodes corresponding to one bit of the vertical transfer CCD for performing four-phase driving can be located within a unit pixel pitch in the vertical direction.
Although the photoelectric conversion region appears to be divided by the lead parts of one of the two vertical transfer electrodes, each having two-layer electrodes, the signal charges stored in the photoelectric conversion region are added at the time of reading of the charge to the vertical transfer CCD section or after the reading of the charge to the vertical transfer CCD section. As a result, a progressive-scan reading operation can be realized by which the signal charges stored i

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