Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-08-17
2002-06-11
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S223000, C257S232000, C257S233000, C438S060000, C438S075000
Reexamination Certificate
active
06403994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of fabricating the same.
2. Description of the Related Art
As one of solid-state imaging devices, a solid-state imaging device having a so-called “vertical overflow drain structure” is well known, in which excess charges in light-receiving sections (sensor sections) are drained toward a substrate.
The present applicant for the invention has disclosed a solid-state imaging device having the vertical overflow drain structure in which a depletion region in a light-receiving section is made of a high-resistivity epitaxial layer with a thickness of 2 &mgr;m or more so that the solid-state imaging device has sensitivity also in the near infrared range (refer to Japanese Unexamined Patent Application Publication No. 9-331058).
FIG. 9
shows the solid-state imaging device described above.
A solid-state imaging device
51
includes a semiconductor substrate
52
composed of a first conductive type, for example, n-type, silicon, and an epitaxial layer
53
of the same conductive type with a low impurity concentration (i.e., n
−
) formed on the semiconductor substrate
52
. The semiconductor substrate
52
and the epitaxial layer
53
constitute an n-type semiconductor base
60
. A first semiconductor well region
54
of a second conductive type, for example, p type, which acts as an overflow barrier region, is formed within the epitaxial layer
53
of the semiconductor base
60
. A high-resistivity semiconductor region, i.e. a so-called high-resistivity epitaxial layer
55
, having a higher resistivity than that of the first p-type semiconductor well region
54
, is formed on the first p-type semiconductor well region
54
by epitaxial growth.
The high-resistivity epitaxial layer
55
has a thickness of 2 &mgr;m or more, preferably, 5 &mgr;m or more, and is composed of a p-type region or an n-type region having a lower concentration than that of the first p-type semiconductor well region
54
, or a non-doped (intrinsic semiconductor) region.
An n
+
semiconductor region
56
and a p
+
positive charge storage region
57
located thereon for constituting each of the light-receiving sections (sensor sections)
61
arrayed in a matrix are formed in vicinity of the surface of the high-resistivity epitaxial layer
55
. An n-type transfer channel region
59
of a vertical transfer register
62
is formed in the high-resistivity epitaxial layer
55
on one side of each column of the light-receiving sections with a read-out gate section
63
therebetween. A second p-type semiconductor well region
58
is formed beneath the transfer channel region
59
. A p-type channel stop region
64
for delimiting the individual light-receiving sections
61
is also formed.
A transfer electrode
66
composed of, for example, polycrystalline silicon, is formed on the transfer channel region
59
, the channel stop region
64
, and the read-out gate section
63
, with a gate insulating film
65
therebetween. The transfer channel region
59
, the gate insulating film
65
, and the transfer electrode
66
constitute the vertical transfer register
62
having a CCD structure. A shading film
67
is formed over the entire surface excluding the aperture of each light-receiving section
61
with an interlayer insulating film
68
covering the transfer electrode
66
therebetween.
In such a manner, the CCD solid-state imaging device
51
having the vertical overflow drain structure is constructed, in which the light-receiving section
61
, the first p-type semiconductor well region
54
acting as the overflow barrier region, and the substrate
52
acting as an overflow drain are formed in the vertical direction.
In the CCD solid-state imaging device
51
, the overflow barrier region
54
is formed at a depth which allows infrared rays to be sufficiently absorbed, and as the high-resistivity epitaxial layer
55
reaching the overflow barrier region
54
becomes depleted, sensitivity is provided also for the near infrared range.
In the CCD solid-state imaging device
51
, for example, in order to obtain desired characteristics of the CCD solid-state imaging device
51
, the high-resistivity epitaxial layer
55
is occasionally formed as an n-type region.
However, when the high-resistivity epitaxial layer
55
is formed as the n-type region, p-type impurities which are ion-implanted in the overflow barrier region
54
before the high-resistivity epitaxial layer
55
is formed may be diffused into the n-type high-resistivity epitaxial layer
55
when the high-resistivity epitaxial layer
55
is formed.
Specifically, as indicated by arrows
70
shown in
FIG. 10
, p-type impurities are diffused along the interface between the high-resistivity epitaxial layer
55
and the n
−
epitaxial layer
53
located therebelow, and consequently, are diffused into a peripheral area other than the pixel area in which the overflow barrier region
54
is not formed.
If the p-type impurities are diffused into the high-resistivity epitaxial layer
55
in the peripheral area as described above, the breakdown voltage of a protection transistor formed in the peripheral area may be decreased, or a leakage current may occur at a pn junction. Consequently, the characteristics of the CCD solid-state imaging device
51
are degraded, resulting in a decrease in the yield during the fabrication.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a solid-state imaging device which has stable characteristics and can be fabricated with a high yield rate, and to provide a method of fabricating the same.
In one aspect of the present invention, a solid-state imaging device includes a second conductive type impurity region formed in a first conductive type semiconductor substrate in an area corresponding to a pixel area, a high-resistivity semiconductor layer of the first conductive type formed on the semiconductor substrate including the impurity region, and an ion-implanted region of the first conductive type formed in at least one of the semiconductor substrate and the high-resistivity semiconductor layer in a peripheral area other than the pixel area.
In another aspect of the present invention, a method of fabricating a solid-state imaging device includes a step of forming an impurity region by doping impurities of a second conductive type in a first conductive type semiconductor substrate in an area corresponding to a pixel area, a step of growing a high-resistivity epitaxial layer of the first conductive type on the semiconductor substrate including the impurity region of the second conductive type, and at least one of a step of ion-implanting impurities of the first conductive type in the first conductive type semiconductor substrate in a peripheral area other than the pixel area and a step of ion-implanting impurities of the first conductive type in the high-resistivity epitaxial layer in the peripheral area.
In accordance with the solid-state imaging device of the present invention, since the ion-implanted region of the first conductive type is provided in the peripheral area, second conductive type impurities diffused from the impurity region of the second conductive type can be inhibited from influencing circuit elements formed in the peripheral area.
In accordance the present invention, since the method of fabricating the solid-state imaging device includes at least one of the step of doping impurities of the first conductive type in the first conductive type semiconductor substrate in the peripheral area and the step of ion-implanting impurities of the first conductive type in the high-resistivity epitaxial layer in the peripheral area, even if second conductive type impurities are diffused from the second conductive type impurity region in the fabrication process, the implanted first conductive type impurities can suppress or cancel the influence of the second conductive type impurities to circuit elements to be formed in the peripheral area.
REFERENCES
Ngo Ngan V.
Rader Fishman & Grauer
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