Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-05-31
2004-04-20
Zarabian, Amir (Department: 2322)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S232000, C257S240000
Reexamination Certificate
active
06724022
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P11-52102 filed May 31, 1999, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having an effective pixel portion and an optical black (OPB) portion arranged in the same column.
Referring to
FIG. 13
, reference numeral
1
generally denotes an interline transfer CCD solid-state imaging device having a vertical optical black portion in the vertical direction of an effective pixel region known as a solid-state imaging device.
The CCD solid-state imaging device
1
has an imaging region
6
composed of an effective pixel region
4
and an optical black pixel portion (which will be hereinafter referred to as OPB portion)
5
for detecting a black level. The effective pixel region
4
has a plurality of photosensor portions
2
arranged in the form of matrix. Each photosensor portion
2
is formed by a photodiode for performing opto-electric conversion of incident light. The effective pixel region
4
further has a plurality of vertical transfer register portions
3
each having a CCD structure, respectively corresponding to the columns of the photosensors
2
in such a manner that each vertical transfer register portion
3
extends along one side of the corresponding column of the photosensor portions
2
. The OPB portion
5
is formed around the effective pixel region
4
as shown by the hatching in
FIG. 13
so as to be optically shielded. The solid-state imaging device
1
further has a horizontal transfer register portion
7
having a CCD structure and a charge detecting portion
8
. Reference numeral
9
denotes a unit effective pixel in the effective pixel region
4
.
The OPB portion
5
has a vertical OPB portion
5
V formed in a vertically extended region of the effective pixel region
4
. The vertical OPB portion
5
V has a portion
10
corresponding to the photosensor portion
2
. This portion
10
and a transfer portion corresponding to one bit of the vertical transfer register portion
3
constitute a unit optical black pixel
11
. The effective pixel
9
and the optical black pixel
11
of the same column commonly have the same vertical transfer register portion
3
.
In the CCD solid-state imaging device
1
, signal charge obtained by opto-electric conversion at the photosensor portion
2
in the effective pixel region
4
and charge at the vertical OPB portion
5
V are read to the vertical transfer register portion
3
at given periods, and then transferred toward the horizontal transfer register portion
7
by four-phase vertical driving clock pulses &phgr;V
1
, &phgr;V
2
, &phgr;V
3
, and &phgr;V
4
(see FIG.
21
), for example. In the horizontal transfer register portion
7
, the charge at the vertical OPB portion
5
V and the signal charge at the photosensor portion
2
both transferred from the vertical transfer register portion
3
are sequentially fed to the charge detecting portion
8
bit by bit by two-phase horizontal driving clock pulses &phgr;H
1
and &phgr;H
2
. In the charge detecting portion
8
, the input charge is converted into voltage, which is then output as a voltage signal.
Referring to
FIG. 21
, T
1
denotes a reading time, and each of &phgr;V
1
and &phgr;V
3
is a ternary pulse having a reading pulse P
1
. &phgr;s denotes an electronic shuttering pulse, and T
2
denotes an exposure time by electronic shuttering.
FIG. 14
is an enlarged plan view of the unit pixel
9
in the effective pixel region
4
shown in
FIG. 13
, and
FIG. 15
is a cross section taken along the line C-C′ in FIG.
14
.
FIG. 16
is an enlarged plan view of the unit optical black pixel
11
in the vertical OPB portion
5
V shown in
FIG. 13
, and
FIG. 17
is a cross section taken along the line E-E′ in FIG.
16
.
This CCD solid-state imaging device
1
is so configured as to have a vertical overflow drain structure.
As shown in
FIGS. 14 and 15
, the effective pixel region
4
has the following structure. A silicon substrate
12
of first conduction type, e.g., n-type, is provided, and a first semiconductor well region
13
of second conduction type, i.e., p-type, is formed on the silicon substrate
12
. An n-type semiconductor region
14
is formed on the upper surface of the first p-type semiconductor well region
13
, and a p
++
positive charge storage region
15
is formed on the upper surface of the n-type semiconductor region
14
, so as to form the photosensor portion
2
. Further, a second p-type semiconductor well region
16
and an n-type transfer channel region
17
are formed in the first p-type semiconductor well region
13
at a position separate from the photosensor portion
2
. A p-type channel stop region
18
is also formed in the first p-type semiconductor well region
13
.
The photosensor portion
2
as a so-called HAD (Hole Accumulation Diode) sensor is formed by the first p-type semiconductor well region
13
, the n-type semiconductor region
14
, and the p
++
positive charge storage region
15
.
The first p-type semiconductor well region
13
functions as a so-called overflow barrier region. A reading gate portion
19
is formed between the photosensor portion
2
and the vertical transfer register portion
3
to be hereinafter described. A p-type semiconductor region
20
is formed in the surface of the substrate at a position corresponding to the reading gate portion
19
.
A transfer electrode
22
of polysilicon, for example, is formed through a gate insulating film
21
on the transfer channel region
17
, the channel stop region
18
, and the p-type semiconductor region
20
of the reading gate portion
19
. The vertical transfer register portion
3
having a CCD structure is formed by the transfer channel region
17
, the gate insulating film
21
, and the transfer electrode
22
.
Further, an interlayer dielectric
23
is formed so as to cover the transfer electrode
22
, and a light shielding film
25
such as an Al film is formed on the entire surface except an opening
24
of the photosensor portion
2
.
As shown in
FIGS. 16 and 17
, the vertical OPB portion
5
V has the following structure. The n-type semiconductor region
14
mentioned above is not formed at the portion
10
corresponding to the photosensor portion
2
, but only the p
++
positive charge storage region
15
is formed on the upper surface of the first p-type semiconductor well region
13
. Thus, no photodiode is formed at the portion
10
. Further, the light shielding film
25
is formed on the entire surface including the portion
10
. The other configuration is similar to that of the effective pixel region
4
, so the corresponding parts are denoted by the same reference numerals and the description thereof will be omitted herein to avoid repetition.
The register width (=W
0
) of the vertical transfer register portion
3
in the effective pixel region
4
is set equal to the register width (=W
0
) of the vertical transfer register portion
3
in the vertical OPB portion
5
V. The gate length (=d
0
) of the reading gate portion
19
in the effective pixel region
4
is set equal to the gate length (=d
0
) of the reading gate portion
19
in the vertical OPB portion
5
V. Further, the area (=a
0
×b
0
) of the photosensor portion
2
in the effective pixel region
4
is set equal to the area (=a
0
×b
0
) of the portion
10
in the vertical OPB portion
5
V.
In the CCD solid-state imaging device
1
mentioned above, the area of the photosensor portion
2
tends to be increased to improve the sensitivity with a reduction in size and an increase in number of pixels. As a result, the area of the vertical transfer register portion
3
is necessarily reduced, and the general dynamic range (corresponding to a so-called maximum handling charge amount) in the CCD solid-state imaging device
1
is determined by t
Rose Keisha
Sonnenschein Nath & Rosenthal LLP
Sony Corporation
Zarabian Amir
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