Solid-state imaging device

Details Solid-state imaging device Solid-state imaging device

2001-11-30

2003-10-28

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S072000, C257S225000, C257S257000, C257S258000, C257S232000, C257S233000, C257S291000, C257S292000, C257S290000, C257S461000

Reexamination Certificate

active

06639293

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state imaging device and to a semiconductor photoelectric conversion device having a photoelectric conversion element such as a photodetector of a photocoupler, and more particularly to a solid-state imaging device that is interchangeable in fabricating processes with a CMOS (Complementary Metal-Oxide Semiconductor) device, i.e., a CMOS image sensor.
2. Description of the Related Art
Recent years have seen the development of cameras that are used for acquiring image data and used together with, for example, personal computers (PCs). Charge coupled device (CCD) image sensors that employ CCDs or CMOS image sensors that are interchangeable with CMOS devices in fabrication processes are used as the solid-state imaging devices that are incorporated in these cameras.
A CCD image sensor is a type of image sensor in which photoelectric conversion elements or photodiodes are arranged two-dimensionally corresponding to pixels (picture elements), the signals of respective pixels that have become electric charges by means of photoelectric conversion elements being read sequentially using vertical transmission CCDs and horizontal transmission CCDs. CMOS image sensors are similar to CCD image sensors in that photoelectric conversion elements are arranged two-dimensionally corresponding to pixels, but in reading signals, rather than using vertical and horizontal transmission CCDs, signals stored for respective pixels are read from selected picture elements by means of selection lines constituted by aluminum lines, as in the read-out of a semiconductor memory device.
In contrast with a CCD image sensor, which requires a plurality of positive and negative power source voltages for driving the CCDs, a CMOS image sensor can be driven by a single power supply and enables lower power consumption and lower power source voltage than a CCD image sensor. Furthermore, the use of a fabrication process for the CCD itself in the fabrication of a CCD image sensor complicates the straightforward application of fabrication processes that are typically used for a CMOS circuit. In contrast, the fabrication processes used for a CMOS image sensor are also commonly used for CMOS circuits. Peripheral circuits such as logic circuits, analog circuits and analog/digital conversion circuits can therefore be formed simultaneously with the CMOS image sensor by means of CMOS fabrication processes that are often used in the fabrication of processors, semiconductor memory devices such as DRAMs (Dynamic Random Access Memories), and logic circuits. In other words, a CMOS image sensor has the advantages that it can easily be formed on the same semiconductor chip as semiconductor memory device or a processor, and in addition, the fabrication of the CMOS image sensor can easily share the same manufacturing plant as a semiconductor memory device or processor.
FIG. 1
is a schematic plan view showing an example of this type of CMOS image sensor and shows the floor plan of a semiconductor device that is formed as a CMOS image sensor. CMOS image sensor
1
is provided with: imaging unit
2
in which photoelectric conversion elements are arranged two-dimensionally for each pixel; timing generator
3
for generating timing signals that are necessary for reading signals from the pixels; vertical scanning unit
4
and horizontal scanning unit
5
for selecting the output of pixels; analog signal processor
6
for amplifying and processing signals from selected pixels; and logic circuit unit
7
for processing the analog signal output from analog signal processor
6
and outputting the result as digital signals. Logic circuit unit
7
is provided with: A/D converter
8
for performing analog-to-digital conversion of the input analog signals; digital signal processor (DSP)
9
for converting the digitized signals to digital image signals; and interface (I/F)
10
for outputting digital image signals to the outside and receiving command data from the outside.
Explanation next regards the unit cells that make up imaging unit
2
of CMOS image sensor
1
. The unit cell in this case is provided for each pixel and is constituted by a photoelectric conversion element, i.e., a photodiode, for each pixel realized by a PN junction, and a transistor that constitutes a switch for selecting this photoelectric conversion element.
FIG. 2
is a schematic sectional view showing the construction of an unit cell of the prior art in a CMOS image sensor.
Unit cell
11
has fundamentally a construction in which a p-type well region
13
is provided on p
−
-type substrate
12
, and n-type photoelectric conversion region
14
which joins p-type well region
13
to form a photodiode is provided in the surface of p-type well region
13
. For the purpose of isolating this unit cell
11
from adjacent unit cells, there is further provided: p
+
-type isolation region
15
that is formed in p-type well region
13
; isolation oxide film
16
formed on, for example, p
+
-type isolation region
15
; gate oxide film
17
which is formed on portions of the surfaces of p-type well region
13
and n-type photoelectric conversion region
14
other than the region in which isolation oxide film
16
is formed; interlayer insulation film
18
which is formed so as to cover the entire surfaces of isolation oxide film
16
and gate oxide film
17
; and shield film
19
which is formed in interlayer insulation film
18
for preventing the incidence of light to unnecessary portions.
In addition, n
+
-type reset drain region
20
is formed in p-type well region
13
at a position that is somewhat separated from n-type photoelectric conversion region
14
. Gate oxide film
17
is also formed on the surface of this n
+
-type reset drain region
20
. Reset transistor
21
is formed which takes the region that is within p-type well region
13
and between n-type photoelectric conversion region
14
and n
+
-type reset drain region
20
as the channel region, n-type photoelectric conversion region
14
as the source region, and n
+
-type reset drain region
20
as the drain region. N-type photoelectric conversion region
14
is thus connected to n
+
-type reset drain region
20
by way of reset transistor
21
.
Unit cell
11
is further provided with driver transistor
22
of a source follower, and transistor
23
, which is a horizontal selection switch. N-type photoelectric conversion region
14
is connected to the gate of driver transistor
22
for outputting to the outside output changes according to the amount of incident light. Load transistor
24
of a source follower is formed for each row of the unit cell array. Driver transistor
22
, transistor
23
, and load transistor
24
are inserted in that order in a series between power supply voltages V
DD
and V
SS
. The voltage output V
out
of this unit cell
11
is obtained from the connection point between transistor
23
and load transistor
24
.
A CMOS image sensor of this construction operates as follows.
First, raising a pulse which is applied to the gate of reset transistor
21
to a high level sets the potential of n-type photoelectric conversion region
14
to the power supply voltage V
DD
which is applied to n
+
-type reset drain region
20
and thus resets the signal charge in n-type photoelectric conversion region
14
. Lowering the pulse which is applied to the gate of reset transistor
21
to a low level brings about the start of accumulation of signal charge. During accumulation of signal charge, the incidence of light generates electron-hole pairs in the region of the lower portion of n-type photoelectric conversion region
14
, whereupon the electrons are accumulated in the depletion layer below n-type photoelectric conversion region
14
and the holes are discharged through p-type well region
13
. The potential of n-type photoelectric conversion region
14
then changes according to the number of accumulated electrons, and by the operation of the source follower, this cha

Affiliated with

Also associated with

Rating

Solid-state imaging device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Solid-state imaging device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Solid-state imaging device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3158594