Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2001-03-30
2003-01-14
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C348S244000, C348S207110, C348S294000, C257S294000, C257S432000, C257S435000
Reexamination Certificate
active
06507054
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device and a method for manufacturing this device, and more particularly relates to a solid-state imaging device having a charge coupled device, and to a method for manufacturing this solid-state imaging device.
BACKGROUND OF THE INVENTION
Solid-state imaging devices such as a CCD (Charge Coupled Device) generally include interline types and frame transfer types, among others.
With the above-mentioned frame transfer type, a plurality of light receiving elements called pixels are formed on a p-type silicon substrate surface, for example, dividing [the surface] into a light receiving portion and a transfer (accumulation) portion. With the pixels formed in each portion, a gate electrode is formed via a gate insulating film over a substrate, and a positive potential is applied to this gate electrode, which forms potential wells at the surface portion of the substrate, and when the pixels in the light receiving portion are irradiated with light for a specific length of time, a signal charge is generated in proportion to the amount of light, and is accumulated in the potential wells.
When clock voltage pulses of two different timings, for instance, are applied to the gate electrode of a plurality of pixels in a row, the barriers of the potential wells are successively opened and closed, and the signal charges are successively transferred from the light receiving portion to the transfer portion.
The transferred signal charges are outputted by clock [signals] having a different timing from the above-mentioned clock [signals] in a register portion, and can be outputted as video signals through an output amplifier or the like.
Thus, a CCD allows optical signals to be converted into signal charges, and are currently in use in a wide range of industrial and consumer imaging devices.
The above-mentioned CCD or other solid-state imaging device is usually equipped with an overflow drain that sweeps away excess signal charges in order to prevent overflowing signal charges from being trapped in the potential wells of other pixels when the signal charges exceed the capacity of the potential wells. Overflow drains are broadly classified into two groups: vertical overflow drains (VOD) and lateral overflow drains (LOD).
FIG. 3
a
is a cross section of a first conventional example of the above-mentioned lateral overflow drain.
A lateral overflow drain (LOD) is formed such that a channel separation layer (not shown) is divided at the boundary between two adjacent pixels (PC
1
and PC
2
) separated by the channel separation layer.
In these pixel regions (PC
1
and PC
2
), an n-type buried channel
11
that serves as a CCD transfer path is formed in a p-type semiconductor substrate
10
, and a p
+
inversion layer
15
is formed at the surface layer thereof.
The above-mentioned n-type buried channel
11
is formed by communicating with the lateral overflow drain LOD at the boundary of the above-mentioned two pixel regions (PC
1
and PC
2
). An n
+
region
18
is formed in the surface layer of the n-type buried channel
11
in the center of the lateral overflow drain LOD so as to connect with the n-type buried channel
11
. A p-type region
17
into which p-type impurities have been introduced to the extent that complete inversion does not occur is formed on the surface of the n-type buried channel
11
around the annular outer periphery of the n
+
region
18
including the n
+
region
18
and the p
+
inversion layer
15
.
A gate insulating film
20
of silicon oxide is formed over the substrate, an annular gate electrode
33
is formed over the gate insulating film
20
, and a wiring layer
34
composed of aluminum, silicon-containing aluminum, or the like is formed so as to fill an opening CH in the gate insulating film
20
in the center of this annular shape, connect to the n
+
region
18
, and also connect to the gate electrode
33
.
In the above structure, the n
+
region
18
serves as the drain and the n-type buried channel
11
of the pixel regions (PC
1
and PC
2
) as the source, creating a MOS field effect transistor in which the drain and gate are short-circuited and which has an annular channel formation region around the outer periphery of the n
+
region
18
and the gate electrode
33
over the gate insulating film
20
.
FIG.
3
(
b
) is a potential diagram in the direction parallel to the surface of the p-type semiconductor substrate
10
of the lateral overflow drain LOD with the above structure.
The p-type region
17
formed at the boundary of the n
+
region
18
and the n-type buried channel
11
of the pixel regions (PC
1
and PC
2
) forms a barrier (potential barrier) to signal charges, and a well (potential well) is formed in the outer direction thereof (the direction of the pixel regions (PC
1
and PC
2
)), in which signal charges (electrons) are accumulated.
If the signal charges exceed the capacity of the potential well, the excess signal charges go over the barrier formed by the p-type region
17
and are swept away to the n
+
region (drain)
18
.
The method for manufacturing the above-mentioned lateral overflow drain LOD will now be described.
First, as shown in FIG.
4
(
a
), a silicon oxide layer is formed by thermal oxidation, CVD, or another such method over the p-type semiconductor substrate
10
, forming the gate insulating film
20
.
Next, the n-type buried channel
11
is formed by the ion implantation of an n-type conductive impurity D
1
, such as phosphorus, over the entire surface.
Next, as shown in FIG.
4
(
b
), a resist film R
1
is formed by a photolithography process in a pattern that opens up the lateral overflow drain formation region, and a p-type impurity D
2
such as boron is introduced by ion implantation to the extent that complete inversion does not occur, thereby forming the p-type region
17
at the surface layer of the n-type buried channel
11
.
Next, as shown in FIG.
4
(
c
), the resist film R
1
is removed, after which a polysilicon film containing a conductive impurity is formed over the entire surface by CVD, for instance, a resist film (not shown) is formed in the pattern of an annular gate electrode, and etching such as RIE (Reactive Ion Etching) is performed to form the annular gate electrode
33
.
Next, as shown in FIG.
5
(
d
), a resist film R
2
is formed by a photolithography process in a pattern that opens up the region that becomes the drain, an n-type impurity D
3
such as arsenic is introduced by ion implantation, and the n
+
region
18
is formed so as to connect to the n-type buried channel
11
.
The gate electrode
33
is used as a mask in the ion implantation of the above-mentioned n-type impurity D
3
here, so the resist film R
2
is formed in a pattern that covers roughly half of the gate electrode
33
.
Next, as shown in FIG.
5
(
e
), the resist film R
2
is removed, after which a resist film R
3
is formed in a pattern covering the region that becomes the drain, and the surface p
+
inversion layer
15
is formed by the ion implantation of a p-type impurity D
4
. Here, the p-type region
17
is formed in a wider pattern than the gate electrode
33
, and the p-type region
17
is formed so that it protrudes from under the gate electrode
33
, and as a result the p
+
inversion layer
15
and the p-type region
17
are connected by a somewhat overlapping portion.
Next, as shown in FIG.
6
(
f
), the resist film R
3
is removed and silicon oxide is deposited over the entire surface covering the gate electrode
33
by CVD, for instance, forming an interlayer insulating film
21
.
Next, a resist film R
4
is formed by a photolithography process in a pattern that opens up the region that becomes the drain, just as with the resist film R
2
.
Next, as shown in FIG.
6
(
g
), the interlayer insulating film
21
and the gate insulating film
20
are etched by RIE or other etching using the resist film R
4
as a mask so as to have a selectivity ratio wit
Adachi Satoru
Gotoh Hiroyuki
Mizobuchi Koichi
Brady W. James
Ho Hoai
Kempler William B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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