Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
1999-07-16
2001-11-13
Lee, John R. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S294000
Reexamination Certificate
active
06316760
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state imaging apparatus applied to a video camera, a monitor camera, and the like. More particularly, the present invention relates to a solid-state imaging device utilizing a charge transfer function.
2. Description of the Related Art
Solid-state imaging apparatuses are applied to camera systems such as video cameras, monitor cameras, cameras at doors for monitoring visitors, car cameras, cameras for TV phones, cameras for multimedia use, and the like. In recent years, reduction of the size, weight, applied voltage, and cost of such solid-state imaging apparatuses have been requested. In order to realize these requests, the solid-state imaging apparatus generally uses a charge coupled device (CCD). The CCD converts transferred charges into voltages in a potential-floating diffusion layer called a floating diode, and outputs the voltages to an output circuit while sweeping the waste charges used in the charge-voltage conversion processing out to a reset drain. This sweeping of waste charges is realized by applying a reset gate clock to a reset transistor.
FIGS. 7A and 7B
illustrate a conventional solid-state imaging apparatus
200
:
FIG. 7A
is a plan view illustrating a CCD imaging section of the solid-state imaging apparatus
200
; and
FIG. 7B
is a view illustrating a circuit construction of a charge-voltage conversion portion and the vicinity thereof of the CCD imaging section.
Referring to
FIGS. 7A and 7B
, the conventional solid-state imaging apparatus
200
includes a CCD chip
200
a
which has a function of resolving light from an object to be imaged for each pixel to perform photoelectric conversion and transferring light charges generated by the photoelectric conversion. The CCD chip
200
a
includes a plurality of photodiodes
1
arranged in a matrix on an n-type substrate
10
, vertical CCDs
2
, and a horizontal CCD
3
. The photodiodes
1
convert incident light to electric charges by photoelectric conversion and accumulate the charges generated by the photoelectric conversion. The vertical CCDs
2
are disposed to correspond to respective columns of photodiodes
1
, and transfer the accumulated charges in the vertical direction. The horizontal CCD
3
transfers the charges transferred from the vertical CCDs
2
in the horizontal direction. A charge-voltage conversion section
5
is disposed downstream of the horizontal CCD
3
for converting the charges transferred from the horizontal CCD
3
to voltages. An output circuit
6
is disposed downstream of the charge-voltage conversion section
5
. The output circuit
6
has a source follower structure normally composed of a plurality of stages and serves to decrease an output impedance.
A transfer gate
4
is also provided between each photodiode
1
and the vertical CCD
2
for transferring the charges accumulated in the photodiode
1
to the vertical CCD
2
.
The charge-voltage conversion section
5
, which is formed on the substrate, includes: a floating diode
51
having a charge accumulation region N
1
which accumulates charges transferred from the horizontal CCD
3
and is in a potential-floating state; and a reset transistor
52
for draining the charges accumulated in the charge accumulation region N
1
. The potential value at the charge accumulation region N
1
changes depending on the a mount of accumulated charges. An amplifier
6
a
which constitutes the output circuit
6
amplifies the potential value and outputs an imaging signal to a signal output terminal
50
a
of the CCD imaging section.
The source of the reset transistor
52
is connected to the charge accumulation region N
1
, the gate thereof is connected to a signal terminal
50
c
to which a reset gate Pulse &phgr;
RS
is applied, and the drain thereof is connected to a signal terminal
50
b
to which a reset drain voltage (voltage for charge drain) V
RD
is applied. The signal terminal
50
c
is connected to a supply source
5
c
of the reset gate pulse &phgr;
RS
, and the signal terminal
50
b
is connected to a supply source
5
b
of the reset drain voltage V
RD
.
Partial potential resistors R
1
and R
2
are connected in series between the supply source
5
b
of the reset drain voltage V
RD
and the ground, so that a DC bias voltage V
BS
is generated at the connection point of these resistors. A diode
54
is connected between the connection point of these resistors and the signal terminal
50
c
so that the forward direction is the direction from the connection point toward the signal terminal
50
c.
The reset drain voltage V
RD
is a DC voltage of, for example, 15 V. The gate of the reset transistor
52
is normally applied with a gate application pulse &phgr;
RS
′ obtained by superimposing the DC bias voltage V
BS
on the reset gate clock &phgr;
RS
which is normally driven at 0 V to 5 V.
FIG. 12
shows the voltage relationship between the reset gate clock &phgr;
RS
and the gate application pulse &phgr;
RS
′. For example, under the conditions of V
RD
=15 V, R
1
=10 k&OHgr;, and R
2
=20 k&OHgr;, V
BS
is 10 V. Under these conditions, assuming that the high level and low level of the reset gate clock &phgr;
RS
are 5 V and 0 V, respectively, and the forward voltage of the diode
54
is −0.5 V, the amplitude of the gate application pulse &phgr;
RS
′ is from 9.5 V to 14.5 V.
The resistors R
1
and R
2
and the diode
54
are disposed externally although it is basically possible to mount these components on the chip, for the following reasons. In the case of on-chip formation, the resistors will be constructed so that the internal voltage V
BS
be generated by dividing the resistance of a low-concentration diffusion layer in consideration of current consumption. In this case, if the concentration of the diffusion layer varies during the fabrication process, the value of the internal voltage V
BS
also varies. As for the diode, if the diode is attempted to be formed on the CCD chip, the process becomes complicated because, while the diode is formed by a bipolar process, the CCD chip is basically formed by a MOS process. It is possible to form a transistor in place of the diode. In this case, however, the value of the internal voltage V
BS
still changes due to a variation in fabrication process.
Referring to
FIGS. 8 and 9A
to
9
C, the operation of sweeping waste charges out from the charge accumulation region after charge-voltage conversion will be described.
FIG. 8
shows a timing of a gate clock pulse &phgr;
H1
for the horizontal CCD
3
and the gate application pulse &phgr;
RS
′ for the reset transistor
52
used during the operation of sweeping waste charges.
FIGS. 9A
to
9
C illustrate potential states in a portion ranging from the downstream end of the horizontal CCD
3
to the reset transistor
52
, at times t=t
1
, t=t
2
, and t=t
3
indicated in
FIG. 8
, respectively.
In
FIGS. 9A
to
9
C, the gate clock pulse &phgr;
H1
is applied to two adjacent horizontal transfer gates
3
a
and
3
b.
In general, two adjacent horizontal transfer gates of the horizontal CCD are located on different semiconductor regions discriminated from each other by ion implantation so as to provide a potential gradient. In this case, boron is implanted in the semiconductor region underlying the horizontal transfer gate
3
a.
An output gate
7
is located near the horizontal transfer gate
3
b.
A constant DC voltage V
OG
is applied to the output gate
7
. A charge accumulation region
51
a
of the floating diode is located between the output gate
7
and a gate
52
a
of the reset transistor
52
.
A charge Ch accumulated in the horizontal CCD
3
at t=t
1
is transferred to the diffusion layer (charge accumulation region)
51
a
called a floating diode, which is in a potential-floating state at t=t
2
via the output gate
7
to which the DC voltage V
OG
of about 1 V to 2 V is applied. The potential at the floating diode varies depending on the amount of the tr
Conlin David G.
Dike, Bronstein, et al.
Lee John R.
Pyu Kevin
Sharp Kabushiki Kaisha
LandOfFree
Solid-state imaging apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Solid-state imaging apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Solid-state imaging apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2577961